alc262w-vd2-gr Realtek Semiconductor Corporation, alc262w-vd2-gr Datasheet - Page 34

• Manufacturer Part Number: alc262w-vd2-gr
• Description: 4-channel Dac And 6-channel Adc High Definition Audio Codec
• Manufacturer: Realtek Semiconductor Corporation

Exit from ‘Link Reset’:
100µsec provides time for the codec PLL to stabilize)
last bit of frame SYNC, it means the codec requests an initialization sequence)
7.3.2.
A ‘Codec Reset’ is initiated via the Codec RESET command verb. It results in the target codec being
reset to the default state. After the target codec completes its reset operation, an initialization sequence is
requested.
In ALC262 D version, the extend power state of conforming to Intel low power ECR the function reset
could not initialize the register setting. Host SW needs to send ‘two’ function reset consecutively to reset
all settings.
4-Ch DAC and 6-Ch ADC High Definition Audio Code
BCLK
SYNC
SDOs
SDIs
RST#
If BCLK is re-started for any reason (codec wake-up event, power management, etc.)
Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC
When the codec drives its SDI to request an initialization sequence (when the SDI is driven high at the
Software is responsible for de-asserting RST# after a minimum of 100µsec BCLK running time (the
1
Codec Reset
2
Previous Frame
SYNC is absent
Normal Frame
3
Driven Low
Driven Low
Driven Low
4 BCLK
Figure 17. Link Reset Timing
4
4 BCLK
25
5
Pulled Low
Pulled Low
Pulled Low
Pulled Low
Link in Reset
6
>=100 usec
Track ID: JATR-1076-21
7
>= 4 BCLK
Wake Event
8
ALC262 Series
Initialization Sequence
Normal Frame
SYNC
Datasheet
9
Rev. 1.9