MK50H28DIP ST Microelectronics, Inc., MK50H28DIP Datasheet - Page 22

• Manufacturer Part Number: MK50H28DIP
• Description: Multi Logical Link Frame Relay Controller
• Manufacturer: ST Microelectronics, Inc.

MK50H28
22/64
05:04
03:00
BIT
07
06
PPARM
PLOST
PPRIM
NAME
PAV
10
11
12
13
14
2
3
4
6
7
8
9
PROVIDER PRIMITIVE LOST is set by the MK50H28 when a provider primitive cannot
be issued because the PAV bit is still set from the previous provider primitive. PLOST is
cleared when PAV is cleared or by a Bus RESET. Writing to this bit has no effect.
PROVIDER PRIMITIVE AVAILABLE is set by the MK50H28 when a new provider
primitive has been placed in PPRIM. PAV is READ/CLEAR ONLY and is set by the chip
and cleared by writing a ”1” to the bit or by Bus RESET. Under normal operation the host
should clear the PAV bit after PPRIM is read.
PROVIDER PARAMETER provides additional information about the reason for the
receipt of certain primitives. The following table shows the parameters for the applicable
provider primitives. This field is undefined for other provider primitives.
PROVIDER PRIMITIVE is written by the MK50H228, in conjunction with setting the PAV
bit, to inform the user of link control conditions. Valid Provider Primitives are as follows:
Init Confirmation: Indicates MK50H28 Init Block reading has completed.
Watchdog Timer Expiry Indication: Indicates expiration of TCLK or RCLK watchdog
timer as determined by the value of PPARM (PPARM=1 indicatesTCLK, PPARM=2
indicates RCLK. If PLOST is set it indicates both RCLK and TCLK watchdog timers
expired). This primitive is issued only if enabled by setting CSR5<15:12> bits to
something other than 0.
Alarm Indication: nN2 of the last nN3 LMI events are corrupted in timing or content.
Alarm Clear Indication: Indicates reception of nN3 correct sequential LMI events after
the Alarm Indication. The issueing of Alarm Clear Indication and Alarm Indication
primitives will be re-attempted if PLOST is set, and will be repeated until issued without
PLOST set.
Interrupt Descriptor Ring MISS: Indicates inability to write to the Interrupt Descriptor
Ring due to the SRVC bit not being clear. With PPARM = 0 it indicates a Transmit
Interrupt Ring MISS. With PPARM = 1 it indicates a Receive Interrupt Ring MISS.
Timer nT1 Expiration: Indicates expiration of the timer nT1.
Timer nT2 Expiration: Indicates expiration of the timer nT2.
Counter nN1 Overflow: Indicates that the counter nN1 has overflowed.
Clear New Bit Indicatiojn: This primitive is issued when the sequence number received
in a Status Enquiry frame matches the sequence number sent in the last Full Status
frame.
LMI Frame Transmitted: Indicates that a LMI frame was just transmitted.
LMI Frame Received: Indicates that a LMI frame was just received and stored in the
buffer(s) corresponding to the LMI channel. The PPARM field will indicate the type of
frame received. In Auto LMI mode, a required host response to a received STATUS
ENQUIRY with Report Type of FULL STATUS is to issue an LMI STATUS Request
primitive with UPARM = 0 (STATUS Request with Report Type of FULL STATUS). The
device will not automatically respond to a received STATUS ENQUIRY with Report Type
of FULL STATUS.
Note: If a LMI frame is received while the PAV bit is still set (because a previously
received primitive has not yet been processed by the host), the MK50H28 will set the
PLOST bit and the received LMI frame will be discarded. No counters will be updated.
Aysnchronous STATUS Frame Received: Indicates that an Aysnchronous STATUS
frame was just received. Received Aysnchronous STATUS frames are stored in the LMI
channel buffer without the DLCI header information.
PPARM
0
1
2
3
STATUS ENQUIRY with Report Type of Sequence
Numbers Exchange Only
STATUS ENQUIRY with Report Type of FULL STATUS
STATUS frame received
SVC or UPDATED STATUS frame received
DESCRIPTION
LMI Frame Received