alc888s Realtek Semiconductor Corporation, alc888s Datasheet - Page 28

• Manufacturer Part Number: alc888s
• Description: 7.1+2 Channel High Definition Audio Codec With Two Independent S/pdif-out
• Manufacturer: Realtek Semiconductor Corporation

7.3.
There are two types of reset within an HDA link:
• Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
• Codec Reset. Generated by software directing a command to reset a specific codec back to its default
An initialization sequence is requested after any of the following three events:
1. Link Reset
2. Codec Reset
3. Codec changes its power state (for example, hot docking a codec to an HDA system)
7.3.1.
A link reset may be caused by 3 events:
1. The HDA controller asserts RST# for any reason (power up, or PCI reset)
2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA
controller
3. Software initiates power management sequences. Figure 14, page 21, shows the ‘Link Reset’ timing
including the ‘Enter’ sequence ( ~ ) and ‘Exit’ sequence ( ~ )
Enter ‘Link Reset’:
link reset
the end of the frame
7.1+2 Channel High Definition Audio Codec
w/Two Independent S/PDIF-OUT
Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a
The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low
The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state
All link signals driven by controller and codecs should be tri-state by internal pull low resistors
When the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at
state
Reset and Initialization
Link Reset
20
ALC888S & ALC888SDD
Track ID: JATR-1076-21
Datasheet
Rev. 1.2