rf2052 RF Micro Devices, rf2052 Datasheet - Page 10

• Manufacturer Part Number: rf2052
• Description: High Performance Wideband Rf Synthesizer/vco With Integrated Rf Mixer
• Manufacturer: RF Micro Devices

RF2052
asserted low. Thus the XO will be stable and a clock is immediately available when ENABLE is asserted high, allowing the chip
to assume normal operation. On cold start, or if REFSTBY is programmed low, the XO will need a warm-up period before it can
provide a stable clock. The length of this warm-up period will be dependent on the crystal characteristics.
Serial Interface
The RF2052 is programmed using a 3-wire serial bus. The programming interface supports both write and read operations.
Write
Initially ENX is high and SDATA is high impedance. The write operation begins with the controller starting SCLK. On the first fall-
ing edge of SCLK the baseband asserts ENX low. The second rising edge of SCLK is reserved to allow the SDI to initialize, and
the third rising edge is used to define whether the operation will be a write or a read operation. In write mode the baseband will
drive SDATA for the entire telegram. RF2052 will read the data bit on the rising edge of SCLK.
The next 7 data bits are the register address, MSB first. This is followed by the payload of 16 data bits for a total write mode
transfer of 24 bits. Data is latched into RF2052 on the last rising edge of SCLK (after ENX is asserted high).
Read
Initially ENX is high and SDATA is high impedance. The read operation begins with the controller starting SCLK. The controller is
in control of the SDATA line during the address write operation. On the first falling edge of SCLK the baseband asserts ENX low.
The second rising edge of SCLK is reserved to allow the SDI to initialize, and the third rising edge is used to define whether the
operation will be a write or a read operation. In read mode the baseband will drive SDATA for the address portion of the tele-
gram, and then control will be handed over to RF2052 for the data portion. RF2052 will read the data bits of the address on
the rising edge of SCLK. After the address has been written, control of the SDATA line is handed over to RF2052. One and a half
clocks are reserved for turn-around, and then the data bits are presented by RF2052. The data is set up on the rising edge of
SCLK, and the controller latches the data on the falling edge of SCLK. At the end of the data transmission, RF2052 will release
control of the SDATA line, and the controller asserts ENX high. The SDATA port on RF2052 transitions from high impedance to
low impedance on the first rising edge of the data portion of the transaction (for example, 3 rising edges after the last address
bit has been read), so the controller chip should be presenting a high impedance by that time.
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SDATA
SCLK
ENX
t
EH
Serial Bus Write
t
X
ES
t
EH
> 20ns, t
write
read
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RFSlice latches on
ES
A6
rising edge
>20ns, t
DS
t
>20ns, t
DS
A1
DH
A0
t
> 20ns, t
CWH
t
DH
D15
Preliminary
CWH
t
CWL
D15
D14
> 40ns, t
D13
CWL
>40ns
t
EH
D0
t
ES
Prelim DS080513