rf2052 RF Micro Devices, rf2052 Datasheet - Page 9

• Manufacturer Part Number: rf2052
• Description: High Performance Wideband Rf Synthesizer/vco With Integrated Rf Mixer
• Manufacturer: RF Micro Devices

Example: VCO1 operating at 2220MHz, 23.92MHz reference frequency, the desired effective divider value is:
The N value is set to 92, equal to the integer part of N
by 2
Converting N and NUM into binary results in the following:
So the registers would be programmed:
The maximum N
the frequency step size would be 1.4Hz. The minimum reference frequency that could be used to program a frequency of
2400MHz (using VCO1) is 2400/127, 18.898MHz (approx).
Two PLL programming banks are provided, the first bank is superseded by the label PLL1 and the second bank is superseded
by the label PLL2. For the RF2052 either these banks may be used to the LO frequency, and can be selected using the MODE
pin.
Loop Filter
The PLL may be designed to use an active or a passive loop filter as required. The internal configuration of the chip is shown
below. If the CFG1:LF_ACT bit is asserted high, the op-amp will be enabled. If the CFG1:LF_ACT bit is asserted low, the internal
op-amp is disabled and a high impedance is presented to the LFILT1 pin. The RFSlice evaluation software can assist with loop
filter designs. Because the op-amp is used in an inverting configuration in active mode, when the passive loop filter mode is
selected the phase-detector polarity should be inverted. For active mode, CFG1:PDP=1, for passive mode, CFG1:PDP=0.
Crystal Oscillator
The PLL may be used with an external reference source, or its own crystal oscillator. If an external source (such as a TCXO) is
being used it should be AC-coupled into one of the XO inputs, and the other input should be AC-coupled to ground.
A crystal oscillator typically takes many milliseconds to settle, and so for applications requiring rapid pulsed operation of the
PLL (such as a TDMA system, or Rx/Tx half-duplex system) it is necessary to keep the XO running between bursts. However,
when the PLL is used less frequently, it is desirable to turn off the XO to minimize current draw. The REFSTBY register is pro-
vided to allow for either mode of operation. If REFSTBY is programmed high, the XO will continue to run even when ENABLE is
Prelim DS080513
24
:
EFF
is 127, and the minimum N
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N
EFF
Preliminary
P1_NUM_MSB (or P2_NUM_MSB)=1100 1111 0011 0010
=F
VCO
NUM=0.8093645495 * 2
LFILT1
NUM=1100 1111 0011 0010 1000 0100
P1_NUM_LSB (or P2_NUM_LSB)=1000 0100
1.1V
*R / F
EFF
P1_N (or P2_N)=0 0101 1100
OSC
is 12. The minimum step size is F
EFF
=2220 *1 / 23.92=92.8093645495.
N=0 0101 1100
LF_ACT=TRUE
, and the NUM value is set to the fractional portion of N
24
LFILT2
=13,578,884.
To VCO tuning
LFILT3
OSC
/2
24
. Thus for a 23.92MHz reference,
RF2052
EFF
multiplied
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