k4j55323qf-gc Samsung Semiconductor, Inc., k4j55323qf-gc Datasheet - Page 10

• Manufacturer Part Number: k4j55323qf-gc
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Write Latency
MODE REGISTER SET(MRS)
K4J55323QF-GC
latency, addressing mode, test mode and various vendor specific options to make GDDR3 SDRAM useful for variety of dif-
ferent applications. The default value of the mode register is not defined, therefore the mode register must be written after
EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE (The GDDR3
SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins
A
clock cycles are requested to complete the write operation in the mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state.
The mode register is divided into various fields depending on functionality. The Burst length uses A
(read latency from column address) uses A
for Write latency. Refer to the table for specific codes for various addressing modes and CAS latencies.
The mode register stores the data for controlling the various operating modes of GDDR3 SDRAM. It programs CAS
0
A
BA
BA
0
0
0
0
1
1
1
1
0
1
~ A
0
11
1
0
11
A
0
0
1
1
0
0
1
1
and BA
10
A
EMRS
BA
MRS
n
0
~ A
0
A
0
1
0
1
0
1
0
1
9
0
0
, BA
A
11
1
Write Latency
in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum six
Reserved
Reserved
1
2
3
4
5
6
A
WL
10
A
9
4
~ A
DLL
A
CAS Latency
8
DLL
6
A
0
0
0
0
1
1
1
1
. A
A
0
1
6
8
7
Test Mode
A
0
0
1
1
0
0
1
1
TM
is used for test mode. A
A
DLL Reset
A
5
0
1
7
- 10 -
7
Yes
No
A
0
1
0
1
0
1
0
1
4
Normal
mode
Test
A
6
CAS Latency
CAS Latency
Reserved
Reserved
Reserved
A
8
9
5
6
7
5
8
is used for DLL reset. A
A
4
256M GDDR3 SDRAM
Burst Length
Burst Type
A
0
0
0
0
1
1
1
1
A
BT
A
0
1
2
3
3
A
Burst Type
0
0
1
1
0
0
1
1
Sequential
1
Rev 1.7 (Jan. 2005)
Reserved
A
2
0
A
0
1
0
1
0
1
0
1
Burst Length
~ A
0
9
2
~ A
. CAS latency
A
Burst Length
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
11
are used
4
A
0