k4j55323qf-gc Samsung Semiconductor, Inc., k4j55323qf-gc Datasheet - Page 41

• Manufacturer Part Number: k4j55323qf-gc
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4J55323QF-GC
5. The following states must not be interrupted by any executable command ; COMMAND INHIBIT or NOP commands
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst.
13. Except data termination disable.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific ; If multiple banks are to be precharged, each must be in a valid state for precharging.
9. Left blank
and READs or WRITEs with auto precharge disabled.
Precharge Enabled
Precharge Enabled
must be applied on each positive clock edge during these states.
Accessing Mode : Starts with registration of a LOAD MODE REGISTER command and ends when t
READ or WRITE : Starts with registration of the ACTIVE command and ends the last valid data nibble.
Read w/ Auto- : Starts with registration of an READ command with auto precharge enabled and ends
Write w/ Auto- : Starts with registration of a WRITE command with auto precharge enabled and ends
Precharge All : Starts with registration of a PRECHARGE ALL command and ends when t
Refreshing : Starts with registration of an AUTO REFRESH command and ends when t
Register
when tRP has been met. Once t
when t
has been met. Once t
Once t
Once t
RP
RP
RC
has been met. Once t
is met, all banks will be in the idle state.
is met, the DDR2(x32) will be in the all banks idle state.
MRD
is met, the GDDR3(x32) SDRAM will be in the all banks idle state.
RP
- 41 -
RP
is met, the bank will be in the idle state.
is met, the bank will be in the idle state.
256M GDDR3 SDRAM
Rev 1.7 (Jan. 2005)
RP
RC
is met.
is met.
MRD