dm9000a Davicom Semiconductor, Inc., dm9000a Datasheet - Page 13

• Manufacturer Part Number: dm9000a
• Description: Ethernet Controller With General Processor Interface
• Manufacturer: Davicom Semiconductor, Inc.

6. Vendor Control and Status Register Set
The DM9000A implements several control and status
registers, which can be accessed by the host. These CSRs
Final
Version: DM9000A-17-DS-F01
May 10, 2006
RCSCSR
ETXCSR
Register
RWPAH
RWPAL
EPDRH
TCSCR
BUSCR
EPDRL
TRPAH
LEDCR
TRPAL
CHIPR
ROCR
SMCR
INTCR
GPCR
MPAR
SCCR
TSR II
EPCR
EPAR
BPTR
FCTR
TCR2
TSR I
WCR
MAR
OCR
NCR
RCR
GPR
NSR
TCR
RSR
FCR
PAR
VID
PID
Network Control Register
Network Status Register
TX Control Register
RX Control Register
RX Status Register
Receive Overflow Counter Register
Back Pressure Threshold Register
Flow Control Threshold Register
RX Flow Control Register
EEPROM & PHY Control Register
EEPROM & PHY Address Register
EEPROM & PHY Low Byte Data Register
EEPROM & PHY High Byte Data Register
Wake Up Control Register (in 8-bit mode)
Physical Address Register
Multicast Address Register
General Purpose Control Register (in 8-bit mode)
General Purpose Register
TX SRAM Read Pointer Address Low Byte
TX SRAM Read Pointer Address High Byte
RX SRAM Write Pointer Address Low Byte
RX SRAM Write Pointer Address High Byte
Vendor ID
Product ID
CHIP Revision
TX Control Register 2
Operation Control Register
Early Transmit Control/Status Register
Transmit Check Sum Control Register
Receive Check Sum Control Status Register
LED Pin Control Register
Processor Bus Control Register
INT Pin Control Register
System Clock Turn ON Control Register
TX Status Register I
TX Status Register II
Special Mode Control Register
MII PHY Address Register
Description
Ethernet Controller with General Processor Interface
are byte aligned. All CSRs are set to their default values by
hardware or software reset unless they are specified
00H
01H
05H
06H
07H
08H
09H
0AH
0CH
0EH
0FH
10H-15H
16H-1DH
1EH
1FH
22H
28H-29H
2AH-2BH
2CH
2DH
2FH
30H
31H
32H
33H
34H
38H
39H
50H
02H
03H
04H
0BH
0DH
23H
24H
25H
2EH
Offset
DM9000A
00H
00H
00H
00H
37H
38H
00H
40H
XXH
00H
Determined by
XXH
9000H
19H
00H
00H
00H
00H
00H
61H
00H
00H
00H
00H
00H
00H
00H
XXH
EEPROM
01H
XXH
00H
00H
00H
0CH
0A46H
00H
00H
00H
Default value
after reset
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