dm9000a Davicom Semiconductor, Inc., dm9000a Datasheet - Page 49

• Manufacturer Part Number: dm9000a
• Description: Ethernet Controller With General Processor Interface
• Manufacturer: Davicom Semiconductor, Inc.

10.3 AC Electrical Characteristics & Timing Waveforms
10.3.1 TP Interface
10.3.2 Oscillator/Crystal Timing
10.3.3 Processor I/O Read Timing
*Note：(the default clk period is 20ns)
1. The IO16 is valid when the SD bus width is 16-bit
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Symbol
Symbol
Symbol
T
and the system address is DATA port (i.e. CMD is
high) and the value of INDEX port is memory data
T
T
T
X
2
t
t
T
T
T
T
T
T
T
T
T
TR/F
T
t
PWH
TDC
+T
CKC
PWL
OST
TM
1
2
3
4
5
6
6
7
8
t/T
6
CS#,CMD valid to IOR# valid
IOR# width
System Data(SD) Delay time
IOR# invalid to System Data(SD) invalid
IOR# invalid to CS#,CMD invalid
IOR# invalid to next IOR#/IOW# valid
When read DM9000A register
IOR# invalid to next IOR#/IOW# valid
When read DM9000A memory with F0h register
IOR# invalid to next IOR#/IOW# valid
When read DM9000A memory with F2h register
CS#,CMD valid to IO16 valid
CS#,CMD invalid to IO16 invalid
OSC Clock Cycle
OSC Pulse Width High
OSC Pulse Width Low
100TX+/- Differential Rise/Fall Time
100TX+/- Differential Rise/Fall Time
Mismatch
100TX+/- Differential Output Duty Cycle
Distortion
100TX+/- Differential Output Peak-to-Peak
Jitter
100TX+/- Differential Voltage Overshoot
IO R #
IO 16
SD
C S#,C M D
Parameter
Parameter
→
→
Parameter
T1
←
←
←
←
T7
T3
→
T2
Ethernet Controller with General Processor Interface
→
→
→
39.998
Min.
←
T4
16
16
T5
Min.
3.0
register index.（ex. F0H, F2H, F6H or F8H）
0
0
0
0
→
←
←
Typ.
←
40
20
20
T6
Typ.
T8
Min.
-
-
-
-
-
10
0
0
2
4
1
40.002
Max.
Max.
→
24
24
5.0
0.5
0.5
1.4
5
Typ.
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
%
DM9000A
Max.
3
3
3
3
Conditions
Conditions
50ppm
Unit
clk*
clk*
clk*
ns
ns
ns
ns
ns
ns
ns
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