cl-ps6700 Cirrus Logic, Inc., cl-ps6700 Datasheet
cl-ps6700
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cl-ps6700 Summary of contents
Page 1
... CL-PS7111 can support up to two CL-PS6700 devices, which allows up to two PC Card sockets per system. Addresses and data are passed to the CL-PS6700 through 16 bits of the 32-bit Data bus (D[15:0]). The PC Card socket is effectively isolated by the CL-PS6700. Except for power and ground pins, the pins on the socket only connect to the rest of the system through the CL-PS6700 ...
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... The CL-PS6700 can be programmed to assem- ble/disassemble CL-PS7111 transfers to the width of the PC Card. The CL-PS6700 has read and write buffers that allow posting of both reads and writes. The read queue is single entry; the write FIFO can queue up to four CL-PS7111 transactions ( bytes) ...
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... Low-Power PC Card Controller CONVENTIONS ......................................................................................... 5 1. PIN INFORMATION.................................................................................... 7 1.1 100-Pin VQFP Pin Diagram ....................................................................................... 7 1.2 Pin Listings................................................................................................................. 8 2. PIN DESCRIPTIONS................................................................................ 10 2.1 CL-PS7111-to-CL-PS6700 Interface Signals........................................................... 10 2.1.1 Address/Data Bus Signals ............................................................................ 10 2.1.2 Access Control Signals................................................................................. 12 2.1.3 Interrupt and Abort Signals........................................................................... 13 2.1.4 Clock, Reset, and Sleep Signals .................................................................. 13 2.2 PC Card Interface Signals........................................................................................ 14 2.2.1 Address and Data Signals ............................................................................ 14 2 ...
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... Bus Timing — System Bus ...................................................................................... 35 5.2 Bus Operations ........................................................................................................ 38 6. PACKAGE SPECIFICATIONS ................................................................. 43 7. ORDERING INFORMATION .................................................................... 44 BIT INDEX................................................................................................ 45 INDEX....................................................................................................... TABLE OF CONTENTS PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller November 1997 ...
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... CL-PS6700 Low-Power PC Card Controller CONVENTIONS This section presents conventions, used in this data book. Abbreviations and Acronyms Acronym or Definition Abbreviation CIS card information structure CMOS complementary metal-oxide semiconductor CPU central processing unit DC direct current DMA direct-memory access EPROM erasable/programmable read-only memory FIFO fi ...
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... The use of ‘tbd’ indicates values that are ‘to be determined’, ‘n/a’ designates ‘not available’, and ‘n/c’ indi- cates a pin that is a ‘no connect’ CONVENTIONS PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller November 1997 ...
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... MD[8] [I/O] 17 MD[9] [I/O] 18 MD[10] [I/O] 19 VSS_O 20 MD[11] [I/O] 21 V3V_O 22 MD[12] [I/O] 23 MD[13] [I/O] 24 MD[14] [I/ November 1997 PRELIMINARY DATA BOOK v1.0 CL-PS6700 100-Pin VQFP PCM_A[6] [ VSS_O PCM_A[7] [O] 73 V5V_O 72 71 PCM_A[25] [O] 70 VDD_HI 69 PCM_A[24] [O] 68 ...
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... Pin Listings Table 1-1 lists the pins of the CL-PS6700 in alphabetical order. Table 1-1. Alphabetical Listing Signal Pin Signal Type Name No. Name MD[0] 4 I/O PCM_A[7] MD[1] 5 I/O PCM_A[8] MD[2] 6 I/O PCM_A[9] MD[3] 8 I/O PCM_A[10] MD[4] 10 I/O PCM_A[11] MD[5] 11 I/O PCM_A[12] MD[6] 13 I/O PCM_A[13] MD[7] 14 I/O PCM_A[14] MD[8] 17 I/O PCM_A[15] MD[9] 18 I/O PCM_A[16] MD[10] 19 I/O PCM_A[17] MD[11] 21 I/O PCM_A[18] MD[12] 23 I/O PCM_A[19] MD[13] 24 I/O PCM_A[20] MD[14] 25 I/O PCM_A[21] MD[15] 26 I/O PCM_A[22] PCE_L 30 I PCM_A[23] PCLK 16 I PCM_A[24] ...
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... CL-PS6700 Low-Power PC Card Controller Table 1-2. Numerical Listing Pin Signal Pin Type No. Name No. 1 RESET_L PIRQ_L[ PIRQ_L[ MD[0] I MD[1] I MD[2] I VSS_O – MD[3] I V3V_O – MD[4] I MD[5] I V3V_CORE – MD[6] I MD[7] I VSS_CORE – PCLK I 41 ...
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... PIN DESCRIPTIONS 2.1 CL-PS7111-to-CL-PS6700 Interface Signals The conventions used for the power sources on the CL-PS7111-to-CL-PS6700 interface are listed in Table 2-1. Table 2-1. Power Source Conventions Symbol Power Source sys system pcm PCMCIA VDDhi VDDhi pin a See Section 2.3 on page 17 for details on power and ground pins. ...
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... For card reads, the data phase is deferred until card data has been collected as signaled by PRDY; the data phase is initiated by a second assertion of PCE_L, and the CL-PS6700 drives this bus with read data in the clock following the assertion of PCE_L (if a word read, during the second clock following PCE_L) ...
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... PC Card Chip Enable: This signal, if asserted, enables the strobing of address and data informa- tion between the CL-PS7111 and the CL-PS6700 through the MD bus. For a read from PC Card memory or I/O space, the CL-PS7111 asserts PCE_L during the address phase and (possibly much later) during the data phase of a read transaction. Depending on the transaction, PCE_L is low for between two and fi ...
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... PCLK can be disabled when the PC Card subsystem is not in use. RESET_L I sys This reset signal can be driven by one of the GPIO outputs of the CL-PS7111 system reset active-low input and places all CL-PS6700 registers and outputs in their default power-up/reset condition. PSLEEP_L I sys The CL-PS7111 drives this signal either by the RUN output or by any GPIO ...
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... DMA transfer, this signal is used as a terminal count and is asser ted along with PCM_IOWR_L during the last DMA card write PIN DESCRIPTIONS PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller November 1997 ...
Page 15
... Single-mode. This data wait signal is used by the card to delay completion of an in-progress memory or I/O access cycle sampled by the CL-PS6700 with a flip-flop clocked on the rising edge of PCLK, then fed to the card interface logic. In order to be recognized, this sig- nal must be asserted at least two clocks before the end of the command strobe. ...
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... I/O Mode: PCM_BVD[2] becomes SPKR_L, the Audio Digital Waveform signal, while PCM_BVD[1] becomes the STSCHG_L signal, a status line that indicates state changes of BVD, CD, and WP. The state of the BVD inputs can be read by the CPU in the CL-PS6700 Status registers and are also available on the PC Card registers. ...
Page 17
... V3V_O sys power plane (V3V_Core). V5V_O pcm Power to PC Card interface I/O buffers; either This pin should be tied to the highest voltage in the system (as seen by CL-PS6700; either 3.3 VDD_HI VDDhi V). VSS_Core Ground pins for the core and input buffers. VSS_O Ground pins for output buffers ...
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... The CL-PS7111 communicates with the CL-PS6700 through the memory bus. This bus has a special mul- tiplexed mode that uses 16 bits of the data bus to transfer address and data messages to the CL-PS6700. This split transaction bus supports posting a (single) read transaction so that the potentially long access time Card does not disrupt the memory bus. The protocol defi ...
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... The CL-PS6700 can be programmed to assemble/disassemble the CL-PS7111 transfers to the width of the PC Card. The CL-PS6700 has read and write buffers, allowing posting of both reads and writes. The read queue is single entry, and the write FIFO can queue up to four CL-PS7111 transactions ( bytes) ...
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... The software can enter Idle State explicitly by setting the Idle mode. In this case, access to the CL-PS6700 registers is supported, but PC Card accesses do not propagate to the card and a read fail or write fail event can occur, which can generate an interrupt to the host. ...
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... The upper 16 bits of register reads should be treated as undefined. The CL-PS6700 registers are accessible in all power states where the CL-PS6700 is powered and has a running PCLK (regardless of the state of PRDY). PC Card access should be done only when the CL-PS6700 is in Active mode. ...
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... NOTE: The three Reserved Interrupt registers must be written with all ones (32’hFFFFFFFF) before interrupts can be captured and output to the PIRQ[1:0] pins REGISTERS Default Input Level PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller R November 1997 ...
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... CL-PS6700 Low-Power PC Card Controller 4.2 Interrupt Structure Interrupt sources in the CL-PS6700 include card inputs, GPIO pins (PCTL/PDREQ_L), and internal status signals. All interrupts in the CL-PS6700 are edge triggered. There are five register bits that control each interrupt, as shwon in Table 4-1. The Interrupt Status register indicates which interrupt inputs have transitioned (rising edge or falling edge) since they were last cleared (using the Interrupt Clear register). The OR’ ...
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... Monitor Card Power Enable (Bit 5). 0 – Card power is assumed to be always on. 1 – Enable monitoring of power. This bit has no effect on card power or the CL-PS6700 power modes such as Standby and Idle. 5 Card Power Enable. 0 – Outputs state of bits [5:3] of Card Power Control register to the PCTL[2:0] pins. ...
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... CL-PS6700 Low-Power PC Card Controller 4.3.2 Card Power Control Register Bit(s) Description 15:14 VS[2:1] Direction. 0 – Input 1 – Output Input pull–up resistors are weak. During Standby mode the pull–up resistors are disabled. 13:12 VS[2:1] Output Value. 11 GPIO Direction. See Note. 0 – Input 1 – Output 10 GPIO Output Value When Card Power Enable Bit is Low. See Note. ...
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... Transaction Queue Flush. Discard data in queue. 1:0 Reserved REGISTERS (0X0C002000 PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller ) Default R/W – November 1997 – ...
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... DMA Request Input Select. Selects input to be used for DMA handshake between the CL-PS6700 and the card. Currently, there is no dedicated card pin assigned for DMA request. 000 – Disable DMA access 001 – PCTL[2] 010 – PCM_VS[2] 011 – ...
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... Card Reset Output Enable. If this bit is set, PCM_RESET is driven with the value of bit 12. If this bit is cleared, the output is tristated. 10 Card Enable. This bit must be set for the CL-PS6700 to make a card access card access is attempted by the CL-PS7111 while this bit is cleared, a read time–out or WR_FAIL interrupt occurs. ...
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... CL-PS6700 Low-Power PC Card Controller 4.5.2 Card Interface Timing Register 0A Bit(s) Description 15:14 Prescaler Field for Watchdog Timer. 00 – Divide – Divide – Divide by 256 11 – Divide by 8192 13:8 Count Field for Watchdog Timer. Settings 3Fh correspond to values between 1 and 64 times the prescale value. The period starts at the end of the command width period and continues as long as PCM_WAIT_L is low ...
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... Setup PCLK REGISTERS ) (0X0C003800 Count (0X0C003C00) Count constant Count constant PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller Default R/W 00 R/W 1Fh R/W 00 R/W 00h R/W Default R/W 00 R/W 00h R/W 00 R/W 00h R ...
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... CL-PS6700 Low-Power PC Card Controller 4.6 I/O Properties Table 4-2 on page 32 summarizes the CL-PS6700 signals. Conventions for Table 4-2 Acronym Definition Assert H Voltage high L Voltage low Type O Output I Input I/O Bidirectional signal Power Group sys System pcm PCMCIA VDDhi VDD_HI pin a Synchronous Signal S Synchronous signal A Asynchronous signal ...
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... The Idle mode is entered and exited by writing the register bit Idle . In Idle mode most internal clocks are gated off, and only the CL-PS6700 register access is supported. All CL-PS6700 inputs and outputs function normally. b The PCM_BVD[1] input protection can be disabled during Card power-off. ...
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... CL-PS6700 Low-Power PC Card Controller 5. ELECTRICAL SPECIFICATIONS Table 5-1. Absolute Maximum Ratings Description Ambient temperature under bias Storage temperature Voltage on any pin with respect to ground Operating power dissipation Standby state power dissipation Power supply voltage Injection current (latch up) NOTE: Stressing the device above those listed in Absolute Maximum Ratings may cause permanent damage to the component. These are stress ratings only. Functional operation at these or any conditions above those indi- cated in the operational sections of this specifi ...
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... YMMV <20 <20 c YMMV < <35 6 <12 < PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller Unit Conditions V Normal operation a V Normal operation V Normal operation CC V Normal operation mA Normal operation MIN CC mA Normal operation MIN ...
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... CL-PS6700 Low-Power PC Card Controller 5.1 Bus Timing — System Bus Table 5-3. System Bus Timing Parameters Symbol Parameter t PCE_L input setup 1a t PCE_L input hold 1b t PTYPE input setup 2a t PTYPE input hold bus address phase input setup bus address phase input hold ...
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... High-Z a High-Z b low b high b low (DMA terminal count) b high (DMA terminal count) b low setup PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller MIN MAX Unit PCLK 6 ...
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... CL-PS6700 Low-Power PC Card Controller Table 5-4. PC Card Bus Timing Parameters Symbol Parameter t PCM_D to command strobe 14 t PCLK high to PCM_VS output 15c t PCLK high to PCM_VS output driven 15d t PCLK high to PCM_VS output High-Z 15e t PCLK high to PCM_RESET output 19a t PCLK high to PCM_RESET output driven ...
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... ADDR. HI ADDR Figure 5-2. Register Read PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller DATA PHASE CYCLE DATA MSB DATA LSB ...
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... CL-PS6700 Low-Power PC Card Controller Figure 5-3. System Bus: Card Data Read November 1997 PRELIMINARY DATA BOOK v1 ELECTRICAL SPECIFICATIONS 39 ...
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... Figure 5-4. PC Card Bus Read Operation ELECTRICAL SPECIFICATIONS PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller November 1997 ...
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... CL-PS6700 Low-Power PC Card Controller Figure 5-5. PC Card Bus Write Operation November 1997 PRELIMINARY DATA BOOK v1 ELECTRICAL SPECIFICATIONS 41 ...
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... ELECTRICAL SPECIFICATIONS DATA OUT 17a Figure 5-7. Standby Mode Timing PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller 17b November 1997 ...
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... Before beginning any new design with this device, please contact Cirrus Logic for the latest package information November 1997 PRELIMINARY DATA BOOK v1.0 15.56 (0.613) 16.50 (0.650) 13.90 (0.547) 14.10 (0.555) CL-PS6700 100-Pin VQFP Pin 1 Indicator 0.30 (0.012) 0.70 (0.028 ...
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... Contact Cirrus Logic for up-to-date information on revisions ORDERING INFORMATION Temperature range Commercial Package type VQFP (very-tight-pitch plastic quad flat pack PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller † Revision November 1997 ...
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... CL-PS6700 Low-Power PC Card Controller A Auto Disable Card Access on Card Removal 24 Auto Power Down Card on Card Removal 24 on Standby 24 Auto Size I/O Accesses 28 C Card Access Width 28 Card Detect 24 Card DMA Enable 27 Card Enable 28 Card Power Enable 24 Card Reset 28 Card Reset Output Enable 28 ...
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... PCM_A[25:0] 14 PCM_BVD[2:1] 16 PCM_CD_L[2:1] 16 PCM_CE_L[2:1] 14 PCM_D[15:0] 14 PCM_IORD_L 16 PCM_OE_L 14 PCM_RDY 15 PCM_REG_L 15 PCM_RESET 17 PCM_VS[2:1] 17 PCM_WAIT_L 15 PCM_WE_L 14 PCM_WP PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller – November 1997 ...
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... CL-PS6700 Low-Power PC Card Controller pins (cont.) PCTL[2:0] 17 PDREQ_L/GPIO 13 , PIRQ_L[1: PRDY 12 PSLEEP_L 13 PTYPE 12 RESET_L 13 power state active 20 idle 20 standby 20 R register addresses 21 spacing 21 Register Read bus operation. See bus operations registers Card Interface Configuration 17 Card Interface Timing Register 0A 29 Card Interface Timing Register 0B 29 ...
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... FAX: 886/2-718-4526 HONG KONG Tsimshatsui UNITED KINGDOM TEL: 852/2376-0801 London, England FAX: 852/2375-1202 TEL: 44/1727-872424 FAX: 44/1727-875919 ITALY Milan TEL: 39/2-3360-5458 FAX: 39/2-3360-5426 Copyright 1997 Cirrus Logic, Inc. All rights reserved. Publications Ordering: 800/359-6414 (USA) or 510/249-4200 Worldwide Web: http://www.cirrus.com CL-PS6700 446700-001 ...