cl-ps6700 Cirrus Logic, Inc., cl-ps6700 Datasheet - Page 26

• Manufacturer Part Number: cl-ps6700
• Description: Low-power Pc Card Controller For The Cl-ps7111
• Manufacturer: Cirrus Logic, Inc.

4.4 System Interface Registers
4.4.1 System Interface Configuration Register
26
Bit(s)
15:10
1:0
9
8
7
6
5
4
3
2
REGISTERS
Description
Reserved
Enable Active Pull-up on Open-Drain Interrupt Outputs PIRQ_L[1:0]. During Standby,
active pull-up is disabled.
Enable Assembly and Disassembly. If this bit is set, assembly and disassembly of card
accesses by CPU or DMA is allowed. When this bit is cleared, the card transaction size is lim-
ited to the width of the card defined by the Card Interface Configuration register bit 7.
Enable Handshake Using Card Ready Signal. When this bit is set, a low-level on PCM_RDY
prevents access to the card. When this bit is cleared, RDY is ignored, but can still generate
interrupts.
Report Read Failure. When this bit is set, a read failure generates an RD_FAIL interrupt.
Read failure can occur due to a time-out condition. Normally, this bit should be cleared so the
CL-PS7111 reports read failures.
Endian Conversion Enable.
0 – Disable byte swapping
1 – Enable byte swapping
PC Cards are defined as little–endian, while the ARM CPU inside the CL-PS7111 can be
big–endian or little–endian.
Transaction Queue Enable. When this bit is set, it enables queuing one or more CL-PS7111
write operations. If this bit is cleared, then PRDY goes low after a write until the write is com-
plete.
Transaction Queue Threshold Control.
0 – FIFO THLD interrupt when two entries are free in queue.
1 – FIFO THLD interrupt when four entries are free in queue.
Transaction Queue Flush. Discard data in queue.
Reserved
C
I R R U S
L
O G I C
C
O N F I D E N T I A L
(0X0C002000
, N D A R
PRELIMINARY DATA BOOK v1.0
)
E Q U I R E D
Low-Power PC Card Controller
November 1997
CL-PS6700
Default R/W
00
–
0
1
1
1
1
1
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–