cl-ps6700 Cirrus Logic, Inc., cl-ps6700 Datasheet - Page 21

• Manufacturer Part Number: cl-ps6700
• Description: Low-power Pc Card Controller For The Cl-ps7111
• Manufacturer: Cirrus Logic, Inc.

CL-PS6700
Low-Power PC Card Controller
4. REGISTERS
The CL-PS6700 registers are spaced at 1-Kbyte boundaries and must be accessed by the CPU in word
mode (not byte mode), even though they are all 16 bits or less in actual width. The upper 16 bits of register
reads should be treated as undefined. The CL-PS6700 registers are accessible in all power states where
the CL-PS6700 is powered and has a running PCLK (regardless of the state of PRDY). PC Card access
should be done only when the CL-PS6700 is in Active mode.
Since register access circumvents the CL-PS6700 write queue, control of register bits, which can affect
posted writes or prefetch reads such as applying and removing card power, should be done only after
checking that the CL-PS6700 is idle using the Idle bit in the Interrupt Input Level register.
4.1 Register Addresses
The following address conventions are used in the register tables.
The tables show the offset from the base addresses. In a CL-PS7111 based system, the CL-PS6700
address spaces start with base addresses 0x4000_0000 for the first PC Card socket (that is, the one con-
nected to NCS[4]), and 0x5000_0000 for the second CL-PS6700 (connected to NCS[5]). To calculate the
address for any register, add the offset (for example, 0X0C00_2800 for the Power Management register)
to the base (for example, 0x4000_0000 for the CL-PS6700 connected to NCS[4]) to get the address
(0X4C00_2800).
November 1997
0X0C002C00
0X0C003C00
0X0C000C00
Offset from
0X0C002800
0X0C002000
0X0C004000
0X0C004400
0X0C002400
0X0C003000
0X0C003400
0X0C003800
0X0C000000
0X0C000400
0X0C000800
Address
Base
Description
Power Management register
Card Power Control register
System Interface Configuration register
DMA Control register
Device Information register
Card Interface Configuration register
Card Interface Timing register 0A
Card Interface Timing register 0B
Card Interface Timing register 1A
Card Interface Timing register 1B
PC Card Interrupt Status register
PC Card Interrupt Mask register
PC Card Interrupt Clear register
PC Card Interrupt Output Select register
PRELIMINARY DATA BOOK v1.0
C
I R R U S
L
O G I C
C
O N F I D E N T I A L
, N D A R
Default
0x1F00
0x1F00
0x0040
0x1F8
XX
0
0
0
0
0
0
0
0
0
E Q U I R E D
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
REGISTERS
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