mu9c4481l-10dc Music Semiconductors, Inc., mu9c4481l-10dc Datasheet - Page 15

• Manufacturer Part Number: mu9c4481l-10dc
• Description: Lancam 1st Family
• Manufacturer: Music Semiconductors, Inc.

Note: The specific timing requirements for Short, Medium, and Long cycles are given in the Switching Characteristics
LENGTH
Medium
CYCLE
Short
Long
Note: D15 reads back as 0.
Section under the tELEH parameter. For two cycle Command Writes (TCO reg or any instruction with “aaaH” as
the source or destination), the first cycle is short, and the second cycle will be the length given.
RST
15
R
E
S
E
T
=
0
Command Write
MOV reg, reg
TCO reg (except CT)
TCO CT (non-reset, HMA invalid)
SPS, SPD, SFR
SBR, RSC, NOP
MOV reg, mem
TCO CT (reset)
VBC (NFA invalid)
SFT
MOV mem, reg
TCO CT (non-reset, HMA valid)
CMP
VBC (NFA valid)
14
13 12
Must be set
Reserved
=000000
INSTRUCTION SET SUMMARY Continued
11
Table 7: Control Register Bit Assignments
10
Table 6: Instruction Cycle Lengths
9
Command Read
Status register or
16-bit register
48 CAM/16 RAM = 001
32 CAM/32 RAM = 010
48 RAM/16 CAM = 100
32 RAM/32 CAM = 101
16 CAM/48 RAM = 011
16 RAM/48 CAM = 110
64 CAM/0 RAM = 000
CAM/RAM Part.
8
No Change = 111
15
CYCLE TYPE
7
6
Data Write
Comparand register
Mask register
Memory array
Memory array
Comparand register
Mask register
Comp. Mask
(NFA valid)
(NFA invalid)
No Change
5
(not last segment)
(not last segment)
(last segment)
(last segment)
None = 00
MR1 = 01
MR2 = 10
= 11
4
LANCAM 1
AR Inc/Dec
Decrement
No Change
3
Increment
Disable
= 00
= 01
= 10
= 11
2
Data Read
Comparand register
Mask register
Memory array
Must be set
Reserved
1
ST
=00
Family
0
Rev. 1a