mu9c4320l-90tdi Music Semiconductors, Inc., mu9c4320l-90tdi Datasheet - Page 14

• Manufacturer Part Number: mu9c4320l-90tdi
• Description: Mu9c4320l Atmcam
• Manufacturer: Music Semiconductors, Inc.

Next Free Address Register
The 32-bit Next Free Address register holds the
highest-priority address that has its Validity bit set empty
(LOW). System-level prioritization ensures that only the
device with the highest-priority empty address in a
vertically cascaded system will respond to a Read Next
Free Address Register Control state. Bits NF19–16 hold
the device Page address, PA3–0. Bits NF11–0 hold the
next free address value. All other bits are reserved, and are
set LOW. See Table 5 on page 26.
Device Select Register
The 32-bit Device Select register is used for software
selection of the ATMCAM. A particular device is selected
when the value in bits DS3–0 are the same as the Page
Address value PA3–0 and the Device Select Enable bit,
DS8, is set LOW. Setting DS8 HIGH prevents the Device
Select register from enabling the ATMCAM. All other bits
are reserved and should be set LOW. See Table 6 on page
26.
Instruction Register
In Software Control mode, control states are written to the
32-bit Instruction register instead of being fed to the
ATMCAM through the AC11–0 lines. Bits IR11–0 are
equivalent to the AC11–0 lines and the control states they
invoke are identical to those of the Hardware Control
mode. The remaining bits are reserved and should be set
LOW.
The Memory Array
The Memory Array is organized as 4096 32-bit locations.
Location 0000H as the highest-priority location, and
location 0FFFH as the lowest-priority location. Write
cycles to the next free address start at location 0000H
when the ATMCAM is empty, and continue down to
0FFFH when it becomes full.
Each 32-bit location in the CAM array has one extra bit,
the Validity bit, which is used to indicate whether the
location is empty or has valid contents. When the Validity
bit is HIGH, the location is empty and is not compared
during Comparison cycles; when it is LOW the contents
are valid and will be compared during a Comparison
cycle. The Validity bits are set or reset during Write cycles
through the /VB line. The Validity bit of a location is
accessed on the /VB line during a Read cycle. The Validity
bits can be set and reset through control states.The Validity
bits are also used in the generation of the next free address
value.
MU9C4320L ATMCAM
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Memory Access
Data is written to or read from the Memory array either
randomly by address, or associatively by comparison and
next free address. Random addressing can be either direct
with the address on the AC11–0 lines (/AV=LOW) or
indirect with the address held in the Address register.
Memory access is controlled through the control states on
the AC11–0 lines (/AV=HIGH) in Hardware Control
mode, or through the Instruction register in Software
Control mode.
VP Table
The VP Table is a separate area of RAM, organized as
4K x 1 and addressed by the upper order 12 bits of the
comparand which hold the VPI field of the ATM header.
The VP Table is contained in the lowest-priority device,
and is enabled by Configuration Register bit FR24. Each
VP Table location holds a flag bit to indicate whether there
is a VP match at that address. A VP Table value of 0
indicates a match, or hit.
The VP Table is not initialized by hardware or software
resets. Before enabling the VP Table, all VP bits must be
initialized by writing to each bit using the VP Table
control states.
The VP Table is accessed during a Compare cycle. If there
is a match in the CAM, it takes priority over a hit in the VP
Table. The /MV flag goes LOW if there is a match in the
CAM or a hit in the VP Table, the /MF line goes LOW if
there is a match in the CAM. The address fed to the VP
Table can be masked by forcing zeros into the address bits.
The VP Table address mask is held in Configuration
Register bits FR23–12. When there is a VP Table hit and
no match in the CAM, the masked VP Table address is
output on the AA11–0 bus while the VP Page address is
output on the PA3–0 bus.
Chip Select
There are two methods of selecting an ATMCAM: through
Hardware control inputs /CS1 and /CS2, and through
software control using the Data Select register.
Chip Select Inputs
The Chip Select lines /CS1 and /CS2 enable an ATMCAM
to participate in a control cycle. If either /CS1 or /CS2 are
LOW the device is selected. By connecting all the /CS1
lines together in a multi-CAM system, and decoding the
lines to each individual device’s /CS2 line, control states
can operate locally within a single device or globally in all
devices. Control states can be broadcast to all devices
within the system by pulling the /CS1 lines LOW, for
operations such as Write Comparand register; individual
devices can be selected to respond to a control state such
as Write at Address by pulling a single decoded /CS2 line
LOW.
Register Descriptions
Rev. 3