mu9c4320l-90tdi Music Semiconductors, Inc., mu9c4320l-90tdi Datasheet - Page 22

• Manufacturer Part Number: mu9c4320l-90tdi
• Description: Mu9c4320l Atmcam
• Manufacturer: Music Semiconductors, Inc.

Control State:
Mnemonic:
Binary Op Code: XXX nnn 000 110
/W: LOW
Description: Writes data from the DQ31–0 bus to the
Configuration register. The write is masked by the
contents of Mask Register nnn. When nnn=000 no mask is
used; when masking is selected, only bits in the addressed
location that correspond to LOW values in the selected
mask register are updated.
Control State:
Mnemonic:
Binary Op Code: XXX XXX 000 110
/W: HIGH
Description: Reads the contents of the Configuration
register to the DQ31–0 bus.
Control State:
Mnemonic:
Binary Op Code: XXX nnn 001 000
/W: LOW
Description: Writes data from the DQ31–0 bus to the
Device Select register. The write is masked by the contents
of Mask Register nnn. When nnn=000 no mask is used;
when masking is selected, only bits in the addressed
location that correspond to LOW values in the selected
mask register are updated.
Control State:
Mnemonic:
Binary Op Code: XXX XXX 001 000
/W: HIGH
Description: Reads the contents of the Device Select
register to the DQ31–0 bus.
Control State:
Mnemonic:
Binary Op Code: XXX XXX 000 111
/W: HIGH
Description: Reads the contents of the Status register to
the DQ31–0 bus. After a Comparison or Read/Write at
Highest-Priority Matching Address cycle only the
highest-priority device with a match responds to this
control state; in the event of a mismatch, the
lowest-priority device responds. After a random access
Read or Write cycle into the Memory array, RD SR will
take place in any selected device.
Control State:
Mnemonic:
Binary Op Code: XXX nnn 000 101
/W: LOW
Description: Writes data from the DQ31–0 bus to the
Comparand register. The write is masked by the contents
of Mask Register nnn. When nnn=000 no mask is used;
when masking is selected, only bits in the addressed
location that correspond to LOW values in the selected
mask register are updated.
MU9C4320L ATMCAM
/AV: HIGH
/AV: HIGH
/AV: HIGH
/AV: HIGH
AV: HIGH
/AV: HIGH
RD FR
WR DS{MRnnn}
Read Device Select Register
RD CR
RD SR
WR CR{MRnnn}
Write Configuration Register
WR FR{MRnnn}
Read Configuration Register
Write Device Select Register
Read Status Register
Write Comparand Register
PA:AA: n/c
PA:AA: n/c
PA:AA: n/c
PA:AA: n/c
PA:AA: n/c
PA:AA: n/c
Scope: S
Scope: AS
Scope: AS
Scope: AS
Scope: S
Scope: HPD/S
22
Control State:
Mnemonic:
Binary Op Code: XXX XXX 000 101
/W: HIGH
Description: Reads the contents of the Comparand
register to the DQ31–0 bus.
Control State:
Mnemonic:
Binary Op Code: XXX nnn 001 001
/W: LOW
Description: Writes data from the DQ31–0 bus to the
Mask register. If nnn=000 then no data is written.
Control State:
Mnemonic:
Binary Op Code: XXX nnn 001 001
/W: HIGH
Description: Reads the contents of the Mask register to
the DQ31–0 bus. If nnn=000 then the output is undefined.
Data Move
Control State:
Mnemonic:
Binary Op Code: XXX nnn 001 100
/W: LOW
Description: Moves data from the Comparand register to
the memory address defined by the contents of the
Address register. The validity of the location is set by the
state of the /VB input, /VB = LOW: Valid, /VB = HIGH:
Empty. The move is masked by the contents of Mask
Register nnn. When nnn=000 no mask is used; when
masking is selected, only bits in the addressed location
that correspond to LOW values in the selected mask
register are updated.
Control State:
Mnemonic:
Binary Op Code: XXX nnn 001 100
/W: HIGH
Description: Moves data from the memory address
defined by the contents of the Address register to the
Comparand register. The move is masked by the contents
of Mask Register nnn. When nnn=000 no mask is used;
when masking is selected, only bits in the addressed
location that correspond to LOW values in the selected
mask register are updated. Note that the /VB line is not
driven during this operation.
/AV: HIGH
/AV: HIGH
/AV: HIGH
/AV: HIGH
/AV: HIGH
Read Comparand Register
RD CR
Write Mask Register
WR MRnnn
Read Mask Register
RD MRnnn
Move Data from Comparand
Register to Memory Indirect
MOV [AR],CR{MRnnn}
Move Data from Memory to
Comparand Register Indirect
MOV CR,[AR]{MRnnn}
PA:AA: n/c
PA:AA: aaa
PA:AA: n/c
PA:AA: n/c
PA:AA: aaa
Control State Descriptions
Scope: AS
Scope: S
Scope: S
Scope: AS
Scope: AS
Rev. 3