74LVC1G386GV,125 NXP Semiconductors, 74LVC1G386GV,125 Datasheet

IC 3-IN EXCLUSIVE-OR GATE SC74-6

74LVC1G386GV,125

Manufacturer Part Number
74LVC1G386GV,125
Description
IC 3-IN EXCLUSIVE-OR GATE SC74-6
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet

Specifications of 74LVC1G386GV,125

Logic Type
XOR (Exclusive OR)
Number Of Inputs
3
Number Of Circuits
1
Current - Output High, Low
32mA, 32mA
Voltage - Supply
1.65 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
SC-74-6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LVC1G386GV-G
74LVC1G386GV-G
935274998125
1. General description
2. Features
3. Ordering information
Table 1.
Type number
74LVC1G386GW
74LVC1G386GV
Ordering information
Package
Temperature range Name
40 C to +125 C
40 C to +125 C
The 74LVC1G386 provides a 3-input EXCLUSIVE-OR function.
The input can be driven from either 3.3 or 5 V devices. This feature allows the use of
these devices in a mixed 3.3 and 5 V environment.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall
time.
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
74LVC1G386
3-input EXCLUSIVE-OR gate
Rev. 02 — 3 September 2007
Wide supply voltage range from 1.65 to 5.5 V
High noise immunity
Complies with JEDEC standard:
Latch-up performance exceeds 250 mA
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5 V
ESD protection:
SOT363 and SOT457 package
Specified from 40 to +85 C and 40 to +125 C.
24 mA output drive (V
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
HBM EIA/JESD22-A114E exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
SC-88
SC-74A
CC
Description
plastic surface-mounted package; 6 leads
plastic surface-mounted package (TSOP6); 6 leads
= 3.0 V)
Product data sheet
OFF
. The I
Version
SOT363
SOT457
OFF

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74LVC1G386GV,125 Summary of contents

Page 1

EXCLUSIVE-OR gate Rev. 02 — 3 September 2007 1. General description The 74LVC1G386 provides a 3-input EXCLUSIVE-OR function. The input can be driven from either 3 devices. This feature allows the use of these devices ...

Page 2

... NXP Semiconductors 4. Marking Table 2. Marking Type number 74LVC1G386GW 74LVC1G386GV 5. Functional diagram Fig 1. Logic symbol Fig 3. Logic diagram 6. Pinning information 6.1 Pinning Fig 4. Pin configuration 74LVC1G386_2 Product data sheet Marking code mnb143 Fig 2. IEC logic symbol 74LVC1G386 GND 3 B 001aag920 Rev. 02 — 3 September 2007 ...

Page 3

... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol A GND Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

Page 4

... NXP Semiconductors [2] When (Power-down mode), the output voltage can be 5 normal operation. CC [3] For SC-74 and SC-88 packages: above 87.5 C the value Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature ...

Page 5

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter I power-off leakage current OFF I supply current CC I additional supply current CC C input capacitance +125 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage ...

Page 6

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t propagation delay see power dissipation V = GND capacitance [1] Typical values are measured the same as t and PLH PHL [ used to determine the dynamic power dissipation (P ...

Page 7

... NXP Semiconductors Table 9. Measurement points 1. 1.95 V 0.5 2 2.7 V 0.5 2.7 V 1 3.6 V 1 5.5 V 0.5 Test data is given in Table 10. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance Z ...

Page 8

... NXP Semiconductors 13. Package outline Plastic surface-mounted package; 6 leads y 6 pin 1 index DIMENSIONS (mm are the original dimensions UNIT max 0.30 1.1 0.25 mm 0.1 0.20 0.10 0.8 OUTLINE VERSION IEC SOT363 Fig 7. Package outline SOT363 (SC-88) 74LVC1G386_2 Product data sheet scale 2.2 1.35 2 ...

Page 9

... NXP Semiconductors Plastic surface-mounted package (TSOP6); 6 leads y 6 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) UNIT 0.1 1.1 0.40 0.26 mm 0.013 0.9 0.25 0.10 OUTLINE VERSION IEC SOT457 Fig 8. Package outline SOT457 (SC-74) 74LVC1G386_2 Product data sheet scale 3.1 1.7 3 ...

Page 10

... Revision history Document ID Release date 74LVC1G386_2 20070903 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • In current. 74LVC1G386_1 20031104 ...

Page 11

... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

Page 12

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 6 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 14 Abbreviations ...

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