sii1162 Silicon image, sii1162 Datasheet - Page 14

• Manufacturer Part Number: sii1162
• Description: Panellink Transmitter
• Manufacturer: Silicon image

Pin Descriptions
Input Pins
Status Pin
Pin Name
Pin Name
CTL3/A1
HSYNC
VSYNC
MSEN
IDCK+
IDCK-
D10
D11
DE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Pin #
Pin #
48
18
17
16
15
14
13
10
12
11
19
20
21
24
9
8
7
6
5
Type
Type
Out
In
In
In
In
In
In
In
Monitor Sense.
This pin is an open collector output. The behavior of this output depends on whether I
interface is enabled or disabled.
I
A HIGH level indicates a powered on receiver is detected at the differential outputs.
A LOW level indicates a powered on receiver is not detected.
This function can only be used in DC-coupling systems.
I
The output is programmable through the I
An external 5K pull-up resistor is required on this pin for systems without internal pull-up
resistor.
2
2
12-bit pixel bus input.
This bus inputs one-half pixel (12-bits) at every latch both falling and rising edge of the
clock.
Input Data Clock +.
This pin must be used in High Swing Mode for dual edge data latching. In Low Swing
Mode Input clock is sensed differentially (IDCK+ minus IDCK-).
Input Data Clock –.
This clock is only used in low swing mode (VREF = V
clock is sensed differentially (IDCK+ minus IDCK-). In case only IDCK+ is supplied in low
swing mode, tie this pin to the same voltage level (V
Dual clock single edge clocking (using either rising or falling edge of both clock inputs) is
not supported.
Data enable.
This signal is high when input pixel data is valid to the transmitter and low otherwise. It is
critical that this signal have the same setup/hold timing as the data bus.
Horizontal Sync input control signal.
Vertical Sync input control signal.
The use of this multi-function input depends on the setting of ISEL/RST#. This input is
regular high-swing 3.3V CMOS level input, not affected by V
resistor so that if left unconnected, it will be LOW.
ISEL/RST# = LOW
General Purpose Input CTL3 is active, for backward compatibility.
ISEL/RST# = HIGH
A1 is active, this bit is used to set the second bit of the I
C bus is disabled (ISEL/RST# = LOW)
C bus is enabled (ISEL/RST# = HIGH)
10
Description
Description
2
C interface (see register definitions, page 14).
DDQ
DDQ
/2) with VREF pin.
2
SiI 1162 PanelLink Transmitter
/2). In Low Swing Mode Input
C device address.
REF
. It has a weak pull-down
SiI -DS-0081-B
Data Sheet
2
C