sii1162 Silicon image, sii1162 Datasheet - Page 4

• Manufacturer Part Number: sii1162
• Description: Panellink Transmitter
• Manufacturer: Silicon image

Table 1. 12-bit Mode Data Mapping ............................................................................................................... 1
Table 2. DK[1:0] Increments and Effect on Setup and Hold times................................................................ 1
Table 3. Sample Programming Sequence for SiI 1162.................................................................................. 1
Table 4. Recommended Components............................................................................................................ 1
Table 5. Routing Guidelines for DVI Traces................................................................................................... 1
Figure 1
Figure 2. Functional Block Diagram ............................................................................................................... 1
Figure 3. Clock Cycle/High/Low Times in High Swing Mode ......................................................................... 1
Figure 4. Differential Transition Times............................................................................................................ 1
Figure 5.
Figure 6. DE High/Low Times......................................................................................................................... 1
Figure 7. Low Swing Control and Data Setup/Hold Times to IDCK+ Differential Clock ................................ 1
Figure 8. High Swing Control and Data Setup/Hold Times to IDCK+ ............................................................ 1
Figure 9. I
Figure 10. ISEL/RST# Minimum Timing......................................................................................................... 1
Figure 11. Logical Interface Options for 12-bit Mode ..................................................................................... 1
Figure 12. SiI 1162 De-skewing Feature Timing ............................................................................................ 1
Figure 13. I
Figure 14. I
Figure 15. I
Figure 16. I
Figure 17. Voltage Regulation using TL431 ................................................................................................... 1
Figure 18. Voltage Regulation using LM317 .................................................................................................. 1
Figure 19. Decoupling and Bypass Capacitor Placement.............................................................................. 1
Figure 20. Decoupling and Bypass Schematic .............................................................................................. 1
Figure 21. Transmitter Input Series Damping Resistors ................................................................................ 1
Figure 22. Differential Output Source Terminations ...................................................................................... 1
Figure 23. Source Termination Layout Illustration ......................................................................................... 1
Figure 24. Example of Incorrect Differential Signal Routing .......................................................................... 1
Figure 25. Example of Correct Differential Signal Routing............................................................................. 1
Figure 26. Source Termination to DVI Connector Illustration......................................................................... 1
Figure 27. Recommended Hot Plug Connection............................................................................................ 1
Figure 28. E-pad Diagram .............................................................................................................................. 1
Figure 29. 48-pin TSSOP Package Dimensions and Marking Specification ................................................. 1
.
SiI 1162 Pin Diagram....................................................................................................................... 1
VSYNC, HSYNC Delay Times to DE
2
C Data Valid Delay (driving Read Cycle data).............................................................................. 1
2
2
2
2
C Byte Read................................................................................................................................ 1
C Byte Write ................................................................................................................................ 1
C Bus Voltage Level-Shifting using Fairchild NDC7002N .......................................................... 1
C Bus Voltage Level Shifting using Philips GTL 2010................................................................ 1
.................................................................................................... 1
LIST OF FIGURES
LIST OF TABLES
iv
SiI 1162 PanelLink Transmitter
SiI-DS-0081-B
Data Sheet