sii1162 Silicon image, sii1162 Datasheet - Page 6

• Manufacturer Part Number: sii1162
• Description: Panellink Transmitter
• Manufacturer: Silicon image

Functional Block Diagram
PanelLink TMDS Digital Core
The PanelLink TMDS core encodes video information onto three TMDS differential data lines and the differential
clock. The video data is input by the Data Capture Logic Block, as a 12-bit bus, using differential clock with dual
edge or single clock with dual edge. A resistor tied to the EXT_SWING pin is used to control the TMDS swing
amplitude.
I
The SiI 1162 can support either I
capable of running at 400kHz, for communication with the host. This interface is not 5V tolerant. If the switching
levels from the host are not 3.3V, then a voltage level shifter must be used. See Figure 15 or Figure 16 for a
system diagram.
The device may be powered down using the PD# pin or with an internal register. The SiI 1162 is reset using the
ISEL/RST# pin.
A connected display may be detected using the DVI Hot Plug signal, attached to the HTPLG pin or with the
Receiver Sense logic internal to the SiI 1162. The state of the detection, or an interrupt signal indicating a change
of state, may be read from the MSEN bit. For systems with multiple I
the I
In non-I
pull-up or pull-down resistors. The CTL3 pin can also be used for backward compatibility with older Silicon Image
devices. The PD# pin can be used in non-I
registers can be used in I
polarity of the clock or the edge responsible to latch the first pixel of incoming data.
Data Capture Logic
Data is input to the SiI 1162 by way of a 12-bit bus. Logic operations such as inversion and edge swapping can
be set by programmable registers described in I2C Register Definitions section or by setting control pins in non-
I
or Low Swing Mode. In High Swing Mode, only single clock (IDCK+) dual edge is processed. IDCK- is ignored in
High Swing Mode. In Low Swing Mode DVO mode, IDCK+ differential clock dual edge is processed.
2
2
C mode before transmitting over the TMDS lines. Voltage level input on VREF sets the SiI 1162 in High Swing
C Interface, Registers and Configuration Logic
2
C address of the SiI 1162.
2
C mode, de-skew pins DK0 and DK1 can be set to adjust the setup and hold times to the SiI 1162 by
Machine
Slave
I
2
C
2
C mode to put the device in power down. The EDGE pin can be used to control the
2
C mode or non-I
Figure 2. Functional Block Diagram
Configuration
Logic Block
Registers
2
C mode to put the device in power down. Similarly, the PD# bit in the
&
2
C mode. In I
2
2
Data Capture
TMDS Digital
C mode, the SiI 1162 uses a slave I
Logic Block
PanelLink
core
2
C devices, pin A1 can be used to change
SiI 1162 PanelLink Transmitter
EXT_SWING
VREF
SiI-DS-0081-B
2
C interface,
Data Sheet