em636165 Etron Technology Inc., em636165 Datasheet - Page 11

• Manufacturer Part Number: em636165
• Description: 1m X 16 Bit Synchronous Dram Sdram
• Manufacturer: Etron Technology Inc.

Etron Confidential
t
t
CLK
COMMAND
CAS# latency=2
CAS# latency=3
CK2,
CK3,
issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid
data contention, input data must be removed from the DQs at least one clock cycle before the first
read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals t
LDQM/UDQM signals must be used to mask input data, starting with the clock edge following the
last data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll
command is entered (refer to the following figure).
CLK
COMMAND
DQ
DQ
DQ
’
’
’
The Read command that interrupts a write burst without auto precharge function should be
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
s
s
s
Write Interrupted by a Read
Write Interrupted by a Write
T0
NOP
T0
NOP
Input data for the write is masked
WRITE A
T1
DIN A
DIN A
WRITE A
T1
DIN A
0
1 Clk Interval
0
READ B
0
don’t care
don’t care
T2
WR
WRITE B
/t
T2
DIN B
CK
rounded up to the next whole number. In addition, the
0
T3
don’t care
NOP
(Burst Length = 4, CAS# Latency = 2, 3)
11
(Burst Length = 4, CAS# Latency =2, 3)
T3
DIN B
NOP
T4
DOUT B
1
NOP
T4
DIN B
NOP
0
T5
DOUT B
DOUT B
2
NOP
Input data must be removed from the
DQ
Read data appears on the outputs to avoid
data contention
T5
DIN B
’
NOP
1
s at least one clock cycle before the
0
T6
DOUT B
DOUT B
3
NOP
T6
NOP
2
1
DOUT B
T7
DOUT B
Rev. 3.4
NOP
T7
EM636165
NOP
3
2
T8
DOUT B
NOP
T8
NOP
Apr. 2008
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