UPD16498P NEC [NEC], UPD16498P Datasheet - Page 64

• Manufacturer Part Number: UPD16498P
• Description: 1/128 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM
• Manufacturer: NEC [NEC]

6.12 Display Memory Access Register (R11)
is written directly to the display RAM. When this register is read-accessed, data from the display RAM is first latched to this
register before being sent to the bus during the next read operation. Accordingly, one dummy read access is required after
display RAM access has been set.
Default settings (initial values set by reset command)
6.13 Display Start Line Setting Register (R12)
Default settings (initial values set by reset command)
6.14 Blink X Address Register (R13)
automatically incremented each time the blink data RAM is accessed.
Default settings (initial values set by reset command)
The display memory access register is used when accessing the display RAM. When this register is write-accessed, data
When using reset connand to reset, the contents of memory are retained.
Display start line set specifies the top line in the display.
The blink X address register specifies the X address of the blink data RAM accessed by the CPU. This address is
RS
RS
RS
D
D
D
64
1
1
1
7
7
7
D
D
D
D
D
D
D
0
7
7
6
7
6
7
6
DSL6
D
D
D
D
D
D
D
0
6
6
5
6
5
6
5
DSL5
D
D
D
D
D
D
D
0
5
5
4
5
4
5
4
DSL4
D
D
D
D
D
D
D
0
0
4
4
3
4
3
4
3
DSL3
BXA3
D
D
D
D
D
D
D
Data Sheet S15730EJ2V0DS
0
0
3
3
2
3
2
3
2
DSL2
BXA2
D
D
D
D
D
D
D
0
0
2
2
1
2
1
2
1
DSL1
BXA1
D
D
D
D
D
D
D
0
0
1
1
0
1
0
1
0
DSL0
BXA0
D
D
D
D
0
0
0
0
PD16498