UPD30121 NEC [NEC], UPD30121 Datasheet - Page 12

• Manufacturer Part Number: UPD30121
• Description: VR4121TM 64-/32-BIT MICROPROCESSOR
• Manufacturer: NEC [NEC]

12
RxD
CTS#
DCD#/
GPIO15
DSR#
TxD/
CLKSEL2,
RTS#/
CLKSEL1,
DTR#/
CLKSEL0
(5) RS-232C interface signals
Notes 1. Do not set CLKSEL (2:0) = 111.
Signal
2. The settings CLKSEL (2:0) = 110 and 101 are only guaranteed for the 168 MHz model. Do not apply
these settings to the 131 MHz model.
I/O
I/O
I
I
I
I
This is a receive data signal. It is used when the RS-232C controller sends serial data to the V
This is a transmit enable signal. Assert this signal when the RS-232C controller is ready to receive
transmission of serial data.
This is a carrier detection signal. Assert this signal when valid serial data is being received. It is also
used when detecting a power-on factor for the V
When this pin is not used for DCD# signal, this pin can be used as an interrupt detection function for the
GIU unit.
This is the data set ready signal. Assert this signal when the RS-232C controller is ready to
receive/transmit serial data between the controller and the V
This function differs depending on the operating status.
<During normal operation (output)>
<When RTC reset (input)>
CLKSEL
111
110
101
signal
Signals used for serial communication
Signals (CLKSEL (2:0) signal) used to set the CPU core operation frequency, BUSCLK signal
frequency, and internal bus clock frequency. These signals are sampled when the RTCRST# signal
changes from low level to high level.
The relationships between the CLKSEL (2:0) signal setting and each clock frequency are shown below.
(2:0)
100
011
010
001
000
TxD signal :
This is a transmit data signal. It is used when the V
controller.
RTS# signal :
This is a transmit request signal. This signal is asserted when the V
data from the RS-232C controller.
DTR# signal :
This is a terminal equipment ready signal. This signal is asserted when the V
transmit or receive serial data.
Note 1
Note 2
Note 2
168.5 MHz
147.5 MHz
131.1 MHz
118.0 MHz
frequency
CPU core
98.3 MHz
90.7 MHz
78.6 MHz
operation
(PClock)
RFU
Data Sheet U14691EJ1V0DS00
28.1 MHz
29.5 MHz
32.8 MHz
29.5 MHz
32.8 MHz
30.2 MHz
26.2 MHz
operation frequency
MIN.
RFU
SDRAM/SROM
(VTClock)
56.2 MHz
59.0 MHz
65.5 MHz
59.0 MHz
65.5 MHz
60.5 MHz
52.4 MHz
MAX.
R
RFU
Function
4121.
R
4121 sends serial data to the RS-232C
R
frequency
28.1 MHz
29.5 MHz
32.8 MHz
29.5 MHz
32.8 MHz
30.2 MHz
26.2 MHz
BUSCLK
4121.
TClock
output)
(When
signal
RFU
R
4121 is ready to receive serial
(When 1/4
of TClock)
BUSCLK
requency
7.0 MHz
7.4 MHz
8.2 MHz
7.4 MHz
8.2 MHz
7.6 MHz
6.6 MHz
signal
RFU
R
4121 is ready to
(MasterOut)
frequency
Interrupt
7.0 MHz
7.4 MHz
8.2 MHz
7.4 MHz
8.2 MHz
7.6 MHz
6.6 MHz
control
R
clock
RFU
4121.
PD30121