UPD30121 NEC [NEC], UPD30121 Datasheet - Page 58

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UPD30121

Manufacturer Part Number
UPD30121
Description
VR4121TM 64-/32-BIT MICROPROCESSOR
Manufacturer
NEC [NEC]
Datasheet

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58
Address setup time (to command signal )
Command signal low-level width
Address hold time (from command signal )
Command signal recovery time
ZWS#
ZWS# signal hold time (from command signal )
Data output setup time (to command signal )
Data output hold time (from command signal )
MEMCS16#/IOCS16# sampling start time
MEMCS16#/IOCS16# hold time (from command
signal )
Data input setup time
Data input hold time
(15) High-speed system bus parameter (ZWS#) (1/2)
Notes 1. With the V
Remarks 1. Do not set CLKSEL (2:0) signal
CLKSEL2
Note 1
delay time from command signal
Signal
2. The value of N is set by using the WISAA (0:2) bits of the BCUSPEEDREG register.
1
1
1
1
0
0
0
0
system bus interface.
The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and
DTR#/CLKSEL0 pins).
2. Do not set CLKSEL (2:0) signal
= 111.
= 110, 101 with 131 MHz model.
CLKSEL1
Parameter
Signal
R
1
1
0
0
1
1
0
0
4121, the MEMW# and MEMR# signals are called the command signals for the high-speed
Notes 1, 2
Notes 1, 2
CLKSEL0
Signal
1
0
1
0
1
0
1
0
Note 2
Notes 1, 2
Notes 1, 2
Note 1
Note 1
Note 1
Note 1
Data Sheet U14691EJ1V0DS00
T (ns)
RFU
35
33
30
33
30
33
38
Symbol
t
t
t
t
t
t
t
t
t
t
AVSV2
AVCL
CLCH
CHAV
CHCL
CHZH
DVCL
CHDV
CHSV
CLZL
t
t
DS
DH
WISAA2 Bit
Condition
0
0
0
0
1
1
1
1
WISAA1 Bit
T
0
0
1
1
0
0
1
1
2
T
T
(N + 1)
T
MIN.
– 44
N
N
25
25
0
15
0
0
5
(N – 1)
WISAA0 Bit
29
19
29
0
1
0
1
0
1
0
1
T
(N
MAX.
1)
(TClock)
N
8
7
6
5
4
3
2
1
20
PD30121
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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