74LVC2G38DP,125 NXP Semiconductors, 74LVC2G38DP,125 Datasheet - Page 5

• Manufacturer Part Number: 74LVC2G38DP,125
• Description: IC DUAL 2IN NAND GATE O-D 8TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr

Specifications of 74LVC2G38DP,125

• Logic Type: NAND Gate with Open Drain
• Number Of Inputs: 2
• Number Of Circuits: 2
• Current - Output High, Low: 32mA, 32mA
• Voltage - Supply: 1.65 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74LVC2G38DP-G; 74LVC2G38DP-G; 935274579125

NXP Semiconductors
8. Limiting values
Table 5.
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
[1]
[2]
[3]
9. Recommended operating conditions
Table 6.
74LVC2G38
Product data sheet
Symbol
V
V
V
I
I
I
I
I
T
P
Symbol
V
V
V
T
Δt/ΔV
IK
OK
O
CC
GND
stg
amb
CC
I
O
tot
CC
I
O
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
For TSSOP8 package: above 55 °C the value of P
For VSSOP8 package: above 110 °C the value of P
For XSON8, XSON8U and XQFN8U packages: above 118 °C the value of P
CC
Limiting values
Operating conditions
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
All information provided in this document is subject to legal disclaimers.
Conditions
Active mode
Power-down mode
V
V
V
T
tot
amb
Rev. 8 — 4 November 2010
I
O
O
tot
< 0 V
> V
= 0 V to V
derates linearly with 2.5 mW/K.
derates linearly with 8 mW/K.
= −40 °C to +125 °C
CC
Conditions
Active mode
disable mode
Power-down mode
V
V
or V
CC
CC
CC
= 1.65 V to 2.7 V
= 2.7 V to 5.5 V
O
< 0 V
tot
derates linearly with 7.8 mW/K.
Dual 2-input NAND gate; open drain
[1][2]
[1][2]
[1]
[3]
Min
−0.5
−0.5
−0.5
−0.5
−50
-
-
-
−100
−65
-
1.65
0
0
0
-
-
Min
0
−40
74LVC2G38
Max
+6.5
+6.5
+6.5
+6.5
-
±50
±50
100
-
+150
300
© NXP B.V. 2010. All rights reserved.
Max
5.5
5.5
V
5.5
5.5
+125
20
10
CC
Unit
V
V
V
V
mA
mA
mA
mA
mA
°C
mW
V
V
V
ns/V
ns/V
Unit
V
V
°C
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