PLL103-02D PhaseLink (PLL), PLL103-02D Datasheet - Page 3

• Manufacturer Part Number: PLL103-02D
• Description: Standard Clock Buffer (SDRAM And DDR) , 12x2 Ddr, 66 - 170MHz in
• Manufacturer: PhaseLink (PLL)

I2C BUS CONFIGURATION SETTING
I2C CONTROL REGISTERS
1. BYTE 6: Outputs Register (1=Enable, 0=Disable)
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Receiver/Transmitter
Address Assignment
Data Transfer Rate
Data Protocol
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Slave
45, 44
43, 42
39, 38
34, 33
Pin#
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
48
-
-
-
A6
Provides both slave write and readback functionality
Standard mode at 100kbits/s
This serial protocol is designed to allow both blocks write and read from the controller. The
bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred
must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will
terminate the transfer. The write or read block both begins with the master sending a slave
address and a write condition (0xD2) or a read condition (0xD3).
Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte
Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte
Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at
power-up is = (0x09).
1
A5
1
Default
1
0
0
0
1
1
1
1
A4
0
Description
Reserved
Reserved
Enhanced DDR Drive. 1 = Enhanced 25%
Reserved
DDR11T, DDR11C
DDR10T, DDR10C
DDR9T, DDR9C
DDR8T, DDR8C
A3
1
A2
0
A1
0
PLL103-02 Rev.D
A0
1
R/W
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Rev 01/11/01 Page 3