ak8825 AKM Semiconductor, Inc., ak8825 Datasheet - Page 130

• Manufacturer Part Number: ak8825
• Description: Hd/sd Multi Format Video Encoder With 3ch Dac
• Manufacturer: AKM Semiconductor, Inc.

HDYPBPR Delay Control Register (R/W) [Sub Address 0x02]
[Component Video Encoder]
Delay amounts of Y signal and Pb / Pr signals are set.
Sub Address 0x02
HDYPBPR Delay Control Register (R/W) [Sub Address 0x02]
Rev-E-00
bit 0
bit 2
bit 3
bit 4
bit 6
bit 7
BIT
~
~
Reserved
bit 7
0
Register Name
HDYDELAY0
HDYDELAY2
PBPRDLY0
PBPRDLY2
Reserved
Reserved
~
~
PBPRDLY2
bit 6
0
HDY Delay Set bits
C Delay Set bits
Reserved bit
Reserved bit
PBPRDLY1
bit 5
0
PBPRDLY0
R/W
R/W
R/W
R/W
R/W
bit 4
0
Default Value
Luminance signal delay amount is set. It is a delay from SYNC
signal.
Delay amount is set based on 27 MHz clock in 480i / p modes,
and 74.25 MHz in 1080i / 720p modes.
[ HDYDELAY2 : YDELAY1 ] - bit
000 : delay amount 0
001: 1 CLK time is delayed.
010: 2 CLK time is delayed.
011: 3 CLK time is delayed.
111: advance 1 CLK time to output.
110: advance 2 CLK time to output.
101: advance 3 CLK time to output.
100 : reserved
Reserved, write “0 “.
Chroma signal delay amount is set. It is a delay from Luminance
signal.
Delay amount is set, based on 27 MHz clock in 480i/p modes, and
74.25 MHz in 1080i / 720p modes.
Both Pb / Pr are delayed by same amount by Delay Amount
setting.
[ PBPRDLY2 : PBPRDLY0 ] – bit
000: delay amount 0
001: 1 CLK time is delayed.
010: 2 CLK time is delayed.
011: 3 CLK time is delayed.
111: advance 1 CLK time to output.
110: advance 2 CLK time to output.
101: advance 3 CLK time to output.
100: reserved
Reserved, write “0 “.
130
Reserved
bit 3
0
HDYDELAY2
bit 2
0
Definition
HDYDEALY1
bit 1
0
Default Value 0x00
HDYDELAY0
bit 0
2008/03
0
[AK8825]