PLL500-27 PhaseLink (PLL), PLL500-27 Datasheet
PLL500-27
Related parts for PLL500-27
PLL500-27 Summary of contents
Page 1
... Low jitter (RMS): 4ps period jitter. 2.25V to 3.63V DC operation. Available in 8-Pin SOIC. DESCRIPTION The PLL500- low cost, high performance and low phase noise VCXO for the 20 to 52MHz range, providing less than -130dBc at 10kHz offset at 52MHz. The very low jitter (4 ps RMS period jitter) makes this chip ideal for applications requiring volt- age controlled frequency sources ...
Page 2
... Crystal output pin. - Not connected. I Frequency control voltage input pin. P Ground pin. O Output clock pin. P +3.3V VDD power supply pin. I Output Enable input pin. Tri-states output if low. Enables output if high. I Crystal input pin. SYMBOL PLL500-27 Preliminary Description MIN. MAX 0 0 0.5 V 0.5 O ...
Page 3
... Frequency change with PWSRR Vdd varied +/- 10% 0V VIN 3.3V, -3dB CONDITIONS with capacitive decoupling between VDD and GND. 52MHz @100Hz offset 52MHz @1kHz offset 52MHz @10kHz offset 52MHz @100kHz offset 52MHz @1MHz offset PLL500-27 Preliminary MIN. TYP. MAX 1.15 3 MIN. ...
Page 4
... XIN DD Ouput load of 15pF -12mA 12mA -4mA OHC OH At TTL level Human Body Model SYMBOL MIN. TYP XIN C (xtal PLL500-27 Preliminary MIN. TYP. MAX. 7 2.25 2.4 V – 0 3000 MAX. UNITS 52 MHz 14 pF 500 250 - 30 ...
Page 5
... Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Low Phase Noise VCXO (20MHz to 52MHz) TSSOP Min. Max. - 1.20 0.05 0.15 0.19 0.30 0.09 0.20 2.90 3.10 4.30 4.50 6.20 6.60 0.45 0.75 A1 0.65 BSC e 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL500- PLL500-27 Preliminary TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE S=SOIC Rev 1/09/03 Page 5 ...