PLL500-37 PhaseLink (PLL), PLL500-37 Datasheet

no-image

PLL500-37

Manufacturer Part Number
PLL500-37
Description
, Low Power CMOS Output Vcxo Family
Manufacturer
PhaseLink (PLL)
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PLL500-37BDC-A0
Manufacturer:
PLL
Quantity:
533
FEATURES
DESCRIPTION
The PLL500-27/-37/-47 are a low cost, high perform-
ance and low phase noise, high linearity VCXO fam-
ily for the 27 to 200MHz range, providing less than -
130dBc at 10kHz offset. The very low jitter (2.5 ps
RMS period jitter) makes these chips ideal for appli-
cations requiring voltage controlled frequency
sources. The IC’s are designed to accept fundamen-
tal resonant mode crystals.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
VCXO output for the 27MHz to 200MHz range
- PLL500-27: 27MHz to 65MHz
- PLL500-37: 65MHz to 130MHz
- PLL500-47: 100MHz to 200MHz
Low phase noise (-130 dBc @ 10kHz offset).
CMOS output with OE tri-state control.
Selectable output drive (Standard or High drive).
- Standard: 12mA drive capability at TTL level.
- High: 36mA drive capability at TTL level.
Fundamental crystal input with no multiplication.
Integrated high linearity variable capacitors.
+/- 150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.5ps period jitter.
2.25V to 3.63V DC operation.
Available in 8-Pin SOIC or DIE.
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
XOUT
XIN
VARICAP
XTAL
OSC
VIN
OE
Preliminary
PIN CONFIGURATION
DIE PAD LAYOUT
FREQUENCY RANGE
PLL500-27
PLL500-37
PLL500-47
PART #
CLK
DRIVSEL^
^: Denotes internal Pull-up
GND
VIN
XIN
PLL500-27/-37/-47
1
2
3
4
MULTIPLIER
1
2
3
4
1x
1x
1x
8
8
7
6
5
7
6
5
100 – 200 MHz
65 – 130 MHz
FREQUENCY
27 – 65 MHz
XOUT
OE^
VDD
CLK
Rev 10/20/03 Page 1

Related parts for PLL500-37

PLL500-37 Summary of contents

Page 1

... Low Power CMOS Output VCXO Family (27MHz to 200MHz) FEATURES VCXO output for the 27MHz to 200MHz range - PLL500-27: 27MHz to 65MHz - PLL500-37: 65MHz to 130MHz - PLL500-47: 100MHz to 200MHz Low phase noise (-130 dBc @ 10kHz offset). CMOS output with OE tri-state control. Selectable output drive (Standard or High drive). ...

Page 2

... O Output clock pin. 455.726 P +3.3V VDD power supply pin. Only one VDD pin is necessary. Output Enable input pin. Tri-states output if set to ‘0’. 626.716 I Enables output if set to ‘1’. Internal pull-up. 888.881 I Crystal output pin. SYMBOL V PLL500-27/-37/-47 Description MIN. MAX 0 0.5 V 0.5 I ...

Page 3

... Phase Noise relative to carrier Phase Noise relative to carrier Note: Preliminary Specifications still to be characterized. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Preliminary SYMBOL CONDITIONS PLL500-27 PLL500-37 PLL500-47 0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load Measured @ 1.4V SYMBOL CONDITIONS From power valid ...

Page 4

... PARAMETERS Crystal Loading Rating (VIN = 1.65V) Maximum Sustainable Drive Level Operating Drive Level Max C0 for PLL500-27 Max C0 for PLL500-37 Max C0 for PLL500-47 C0/C1 ESR Note: The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above. If the crystal requires more load nominal frequency, the additional load must be added externally. ...

Page 5

... Order Number PLL500-27SC-R PLL500-27DC PLL500-37SC-R PLL500-37DC PLL500-47SC-R PLL500-47DC PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur- nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’ ...

Related keywords