PLL500-10 PhaseLink (PLL), PLL500-10 Datasheet
PLL500-10
Related parts for PLL500-10
PLL500-10 Summary of contents
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... Low jitter (RMS): 2.5ps period jitter. 2.25V to 3.63V DC operation. Available in die. DESCRIPTION The PLL500- low cost, high performance and low phase noise VCXO for the 8 to 40MHz range, providing less than -130dBc at 10kHz offset at 30MHz. The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring volt- age controlled frequency sources ...
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... Output Enable input pin. Tri-states output if low. Enables output if high. P Ground pin. O Output clock pin. P +3.3V VDD power supply pin. I Divider select input pin. Allows user to choose between divider Crystal input pin. SYMBOL PLL500-10 Preliminary Description MIN. MAX 0 0 ...
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... Frequency change with PWSRR Vdd varied +/- 10% 0V VIN 3.3V, -3dB CONDITIONS with capacitive decoupling between VDD and GND. 30MHz @100Hz offset 30MHz @1kHz offset 30MHz @10kHz offset 30MHz @100kHz offset 30MHz @1MHz offset PLL500-10 Preliminary MIN. TYP. MAX 1.15 3 MIN. ...
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... Ouput load = 15pF DD 17.664MHz, Ouput load = 15pF -12mA 12mA -4mA OHC OH At TTL level Human Body Model SYMBOL MIN. TYP XIN C (xtal PLL500-10 Preliminary MIN. TYP. MAX. 3.2 2.2 2.25 2.4 V – 0 3000 MAX. UNITS 40 MHz 8 pF 500 250 - ...
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... TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL500- PLL500-10 Preliminary TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE D=Die Rev 3/24/03 Page 5 ...