PLL601-02 PhaseLink (PLL), PLL601-02 Datasheet
PLL601-02
Related parts for PLL601-02
PLL601-02 Summary of contents
Page 1
... Advanced low power sub-micron CMOS process. 3.3V operation. Available in 16-Pin SOIC or TSSOP. DESCRIPTIONS The PLL601- low cost, high performance and low phase noise clock synthesizer. With PhaseLink’s proprietary analog and digital Phase Locked Loop techniques, the chip accepts 10-27MHz crystal or clock input, and produces outputs clocks up to 160MHz at 3 ...
Page 2
... Output Enable. Tri-state CLK and REFOUT when low. Has internal pull-up. O Buffered crystal oscillator clock output. Controlled by REFEN. I Multiplier Select Pin 0. Determines CLK output. Has internal pull-up. I Multiplier Select Pin 1. Determines CLK output. Has internal pull-up. I Multiplier Select Pin 3. Determines CLK output. Has internal pull-up. P Ground. PLL601-02 Preliminary Description Rev 04/23/01 Page 2 ...
Page 3
... CONDITIONS At 3.3V 0.8V to 2.0V with no load 2.0V to 0.8V with no load At VDD/2 With capacitive decoupling between VDD and GND With capacitive decoupling between VDD and GND 100Hz offset, 3.3V 1kHz offset, 3.3V 10kHz offset, 3.3V 100kHz offset, 3.3V PLL601-02 MIN. MAX. UNITS - 0 0.5 V 0.5 CC ...
Page 4
... 25mA -8mA Load OE, Select Pins IN SYMBOL CONDITIONS Parallel Fundamental Mode F XIN C (xtal) L PLL601-02 Preliminary MIN. TYP. MAX. 3.135 3.465 2 0.8 VDD/2 (VDD/2) 1 VDD/2 (VDD/2) 2.4 0.4 VDD-0.4 35 120 5 MIN. TYP. MAX Rev 04/23/01 Page 4 UNITS V ...
Page 5
... Low Phase Noise PLL Clock Multiplier TSSOP Min. Max. - 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 A1 0.65 BSC e 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL601- PLL601-02 Preliminary TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE S=SOIC, O=TSSOP Rev 04/23/01 Page 5 ...