CY28510OC SPECTRALINEAR [SpectraLinear Inc], CY28510OC Datasheet - Page 8

• Manufacturer Part Number: CY28510OC
• Description: Peripheral I/O Clock Generator
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

Rev 1.0, November 20, 2006
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This means the total capac-
itance on each side of the crystal must be 2 times the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors
CL ................................................... Crystal load capacitance
CLeActual loading seen by crystal using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs .............................................Stray capacitance (trace,etc)
Ci .............Internal capacitance (lead frame, bond wires etc)
Layout and Decoupling Consideration
The V
not connected internally. What this implies is that each group
Load Capacitance (each side)
DD
nets for each of the subgroups within each group are
Ce = 2 * CL - (Cs + Ci)
Cs1
Figure 2. Crystal Loading Example
Ce1
X1
Ci1
CLe
Clock Chip
XTAL
Total Capacitance (as seen by the crystal)
=
(
Ce1 + Cs1 + Ci1
Ci2
crystal must be 2 times the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
(Ce1,Ce2) should be calculated to provide equal capacitance
loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
should have a separate V
The more you can avoid external coupling across VDD planes,
the better each sub-net can operate at a different frequency,
whether jitter is on or off, or it is at a different frequency.
X2
Ce2
1
Cs2
3 to 6p
33pF
Trim
Pin
+
1
Trace
2.8pF
Ce2 + Cs2 + Ci2
DD
1
pool and it’s own 0.1 F capacitor.
)
CY28510
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