CY28510OC SPECTRALINEAR [SpectraLinear Inc], CY28510OC Datasheet - Page 9

• Manufacturer Part Number: CY28510OC
• Description: Peripheral I/O Clock Generator
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

Rev 1.0, November 20, 2006
CLK_STOP# Clarification
The CLK_STOP# signal is an active low input used for
synchronous stopping and starting the CLK output clocks
while the rest of the clock generator continues to function.
CLK_STOP# Deassertion
The deassertion of the CLK_STOP# signal will cause all CLK
outputs that were stopped to resume normal operation in a
synchronous manner, synchronous manner meaning that no
CLK_STOP#
CLK_STOP#
CLK Internal
CLK Internal
V D D _ A L L
R E F
C L K
CLK
CLK
2 .0 V
Figure 5. CLK_STOP# Deassertion Waveforms
Figure 4. CLK_STOP# Assertion Waveforms
< 1 .2 m s e c
Figure 3. Power-up Signal Timing
CLK_STOP# Assertion
When CLK_STOP# pin is asserted low, all CLK outputs will be
stopped after being sampled by two rising CLK internal clock
edges.
short or stretched clock pulses will be produced when the
clock resumes. The maximum latency from the deassertion to
active outputs is no more than 2 CLK clock cycles
CY28510
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