88e3015 Marvell Semiconductor, Inc., 88e3015 Datasheet - Page 12

• Manufacturer Part Number: 88e3015
• Description: Integrated 10/100 Fast Ethernet Transceiver
• Manufacturer: Marvell Semiconductor, Inc.

Table 2:
Doc. No. MV-S103657-00, Rev. C
Page 12
8 8E301 5
52
55
54
53
51
50
45
41
47
46
43
42
RGMII Interface
88E30 18
60
63
62
61
59
58
53
49
55
54
51
50
88E3015/88E3018
Integrated 10/100 Fast Ethernet Transceiver
Pin Name
TX_CLK/TXC
TX_CTRL/TX_CTL
TXD[3]/TD[3]
TXD[2]/TD[2]
TXD[1]/TD[1]
TXD[0]/TD[0]
RX_CLK/RXC
RX_CTRL/
RX_CTL
RXD[3]/RD[3]
RXD[2]/RD[2]
RXD[1]/RD[1]
RXD[0]/RD[0]
Document Classification: Proprietary Information
CONFIDENTIAL
Typ e
I
I
I
O
O
O
De scr ip tio n
RGMII Transmit Clock provides a 25 MHz or 2.5
MHz reference clock with ± 50 ppm tolerance
depending on speed. In RGMII mode, TX_CLK is
used as TXC.
RGMII Transmit Control. TX_EN is presented on
the rising edge of TX_CLK. In RGMII mode,
TX_CTRL is used as TX_CTL.
A logical derivative of TX_EN and TX_ER is pre-
sented on the falling edge of TX_CLK.
RGMII Transmit Data. In RGMII mode, TXD[3:0]
are used as TD[3:0].
The transmit data nibble is presented on TXD[3:0]
on the rising edge of TX_CLK.
RGMII Receive Clock provides a 25 MHz or 2.5
MHz reference clock with ± 50 ppm tolerance
derived from the received data stream depending
on speed. In RGMII mode, RX_CLK is used as
RXC.
RGMII Receive Control. RX_DV is presented on
the rising edge of RX_CLK. In RGMII mode,
RX_CTRL is used as RX_CTL.
A logical derivative of RX_DV and RX_ER is pre-
sented on the falling edge of RX_CLK.
RGMII Receive Data. In RGMII mode, RXD[3:0]
are used as RD[3:0].
The receive data nibble is presented on RXD[3:0]
on the rising edge of RX_CLK.
October 26, 2006, Advance
Copyright © 2006 Marvell