PSMN2R0-30YL_10 NXP [NXP Semiconductors], PSMN2R0-30YL_10 Datasheet - Page 3

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PSMN2R0-30YL_10

Manufacturer Part Number
PSMN2R0-30YL_10
Description
N-channel TrenchMOS logic level FET
Manufacturer
NXP [NXP Semiconductors]
Datasheet
NXP Semiconductors
PSMN2R0-30YL_3
Product data sheet
Fig 1.
Fig 3.
(A)
I
D
10
10
120
100
(A)
I
10
80
60
40
20
D
3
2
1
0
10
mounting base temperature
Continuous drain current as a function of
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
0
-1
50
(1)
Limit R
100
(1)
DSon
= V
150
DS
All information provided in this document is subject to legal disclaimers.
T
003aac471
/ I
mb
1
D
(°C)
200
Rev. 03 — 7 January 2010
Fig 2.
DC
P
(%)
der
120
80
40
0
function of mounting base temperature
Normalized total power dissipation as a
0
10
N-channel TrenchMOS logic level FET
50
PSMN2R0-30YL
100
V
DS
(V)
100 μs
10 ms
1 ms
100 ms
10 μs
150
© NXP B.V. 2010. All rights reserved.
T
003aac529
mb
03aa16
(°C)
10
200
2
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