STV-5410-R01 STMICROELECTRONICS [STMicroelectronics], STV-5410-R01 Datasheet - Page 10

• Manufacturer Part Number: STV-5410-R01
• Description: Mono and Colour Digital Video CMOS Image Sensors
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

VV5410 & VV6410
note1: The free running qck, slow by default, is enabled by writing 8’h04 to serial register [20].
note2: The contents of the extra black lines are enabled on to the data bus by setting bit [5] of serial register [17]. If bit [0] of serial
register [24] is reset, indicating that the preferred coprocessor device is not the VP3 device, (a STMicroelectronics coprocessor),
then the extra black lines are enabled by default regardless of the basic video mode selected.
The registers that control the image position within the pixel array and also the order in which the pixels are read out have not
been included in the table as their values are subject to a secondary series of registers. We will discuss the former in sections 2.2
and 2.3.
3.1.2
It is recommended that a 16 MHz clock is used to generate CIF-25fps,CIF-30fps and QCIF-60fps and that an 8 MHz clock is used
to generate QCIF-25fps and QCIF-30fps, however the sensor can adapt to a range of other input frequencies and still generate
the required frame rates. For example, a 24 MHz clock can be used to generate CIF-30fps. By setting bit [7] of serial register [22]
the sensor can automatically divide the incoming clock by 1.5 by setting bit [7] of serial register [22], such that the internal clock
generator logic will still receive a 16 MHz clock.
Note that the clock division register is internally an 8 bit value, although the user may only program the lower nibble. The upper
nibble is reserved for setting the clock divisor as we change between primary video modes. The lower nibble can be programmed
to reduce the effective frame rate within each video mode.
The system clock divisor column in Table 5 assumes that the programmable pixel clock divisor is set to the default of 0,
implementing a divide by 1 of the internal pixel clock. Consider the following scenario where a user requires 15 fps CIF resolution
image. As can be seen there are a wide range of options to achieve the same result.
3.2
The physical pixel array is 364 x 296 pixels. The pixel size is 7.5 m by 6.9 m. The image size for NTSC is 306 x 244 pixels, for
PAL and CIF it is 356 x 292 pixels, while for the QCIF modes the image size is 180 x 148 pixels. The remaining 4 physical
columns on each side of the PAL image size prevent columns 1 and 2 in PAL/CIF modes from being distorted by the edge effects
which occur when a pixel is close to the outer edge of the physical pixel array. Please note that these columns can be enabled as
part of the visible image if the user is operating the sensor in the pantilt QCIF mode.
Figure 3 shows how the 306 x 244 and 180 x 148 sub-arrays are aligned within the bigger 364 x 296 pixel array. The Bayer
colourisation pattern requires that the top-left corner of the pixel sub-array is always a Green 1 pixel. To preserve this Bayer
colour pattern the NTSC sub-array has been offset relative to the centre of the array. The QCIF size images are centrally
orientated.
Image read-out is very flexible. Sections 3.3.2 - describe the options available to the user. By default the sensor read out is
configured to be horizontally ‘shuffled’ non-interlaced raster scan. The horizontally ‘shuffled’ raster scan order differs from a
conventional raster in that the pixels of individual rows are re-ordered, with the odd pixels within a row read-out first, followed by
the even pixels. This ‘shuffled’ read-out within a line, groups pixels of the same colour (according to the Bayer pattern - Figure 2)
together, reducing cross talk between the colour channels. This option is on by default and is controllable via the serial interface.
The horizontal shuffle option would normally only be selected with the colour sensor variant, VV6410.
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Pixel Array
Input Clock Frequencies
(MHz)
clk in
12
16
24
8
Divide by 3/2
enabled?
yes
yes
no
no
Table 5 : System clock divisor options
System clock
Commercial in confidence
cd5410-6410f-3-0.fm
divisor
4
4
4
4
Pixel clock
divisor
1
1
2
2
pclk (MHz)
2
2
2
2
Field Rate
Operating Modes
15
15
15
15