CS8140YDW24 CHERRY [Cherry Semiconductor Corporation], CS8140YDW24 Datasheet
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CS8140YDW24
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CS8140YDW24 Summary of contents
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Linear Regulator with ENABLE, Description The CS8140 Watchdog Regulator with protection circuitry and three logic control functions that allow a microprocessor to control its own power supply. The CS8140 is designed for use in automotive, ...
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Input Voltage Operating Range .................................................................................................................................................-0.5 to +26V Peak Transient Voltage (46V Load Dump @ 14V V Electrostatic Discharge (Human Body Model)...............................................................................................................................................4kV WDI Input Signal Range ...............................................................................................................................................-0.3 to +7V Internal Power Dissipation ..............................................................................................................................Internally limited Junction Temperature Range (TJ) .......................................................................................................................-40¡C to +150¡C ...
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PARAMETER RESET Threshold HIGH V V R(HI) LOW V V R(LOW) Threshold Hysteresis(V ) (HIGH - LOW) RH Reset Output Leakage V = HIGH RESET Output Voltage Low ² V L(LOW 2.7k½* Low ( ...
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V vs. V over 25ûC OUT IN LOAD 5 ENABLE IN 5.0 4 LOAD load 4 6.67W load 3 10W 3.0 load 2.5 2.0 1.5 1.0 ...
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Typical Performance Characteristics: continued Quiescent Current vs. V over ENABLE (V) IN Watchdog Frequency ...
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Dropout Voltage The input-output voltage differential at which the circuit ceases to regulate against further reduction in input volt- age. Measured when the output voltage has dropped 100mV from the nominal value obtained at 14V input, dropout voltage is dependent ...
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Figure 3: Timing Diagrams for Watchdog and ENABLE Functions 3a: V when Watchdog is held high and ENABLE = HIGH. OUT V IN ENABLE WDI 0V RESET 0V V OUT 0V 3b: V when Watchdog is held low and ENABLE ...
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As long as ENABLE is high or ENABLE is low and the Watchdog signal is normal, V will (typ). If OUT ENABLE is low and the Watchdog signal moves outside programmable limits, the output transistor turns off ...
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The duration of the reset pulse is given by: T (typ WDI( ) RESET This has a tolerance of ±50% due to the IC, and ±10% due to the capacitor. The duration of the reset pulse ...
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Battery 0.1mF (optional) Ignition 0.1mF *C1 is required if regulator is located far from the power source filter. **C2 required for stability ***R ² 80k½ Figure 7. Application Diagram 110K Figure 8. Applications diagram for CS8140. The ...
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Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case ...
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... REF: JEDEC MS-001 Ordering Information Part Number Description CS8140YT7 7L TO-220 Straight CS8140YTVA7 7L TO-220 Vertical CS8140YTHA7 7L TO-220 Horizontal CS8140YDW24 24L SO CS8140YDWR24 24L SO (tape & reel) CS8140YN14 14L PDIP CS8141YT7 7L TO-220 Straight CS8141YTVA7 7L TO-220 Vertical CS8141YTHA7 7L TO-220 Horizontal CS8141YDWF24 ...