CS8140YDW24 CHERRY [Cherry Semiconductor Corporation], CS8140YDW24 Datasheet - Page 8

• Manufacturer Part Number: CS8140YDW24
• Description: 5V, 500mA Linear Regulator with ENABLE, , and Watchdog RESET
• Manufacturer: CHERRY [Cherry Semiconductor Corporation]

As long as ENABLE is high or ENABLE is low and the
Watchdog signal is normal, V
ENABLE is low and the Watchdog signal moves outside
programmable limits, the output transistor turns off and
the IC goes into SLEEP mode. Only the ENABLE circuitry
in the IC remains powered up, drawing a quiescent cur-
rent of 250µA.
The Watchdog monitors the frequency of an incoming
WDI signal. If the signal falls outside of the WDI window,
a frequency programmable pulse train is generated at the
signal reappears at the lead (ENABLE = HIGH).
The lower and upper window threshold limits of the
watchdog function are set by the value of C
its are determined according to the following equations for
the CS8140:
(a)
(b)
For the CS8141 the lower limit is determined by the equa-
tions in (a) above.
The capacitor C
period.
The
nal is outside of its preset window (Figure 3), when the
regulator is in its power up state (Figure 4a) or when V
drops below V
If the Watchdog signal falls outside of the preset voltage
and frequency window, a frequency programmable pulse
train is generated at the
correct Watchdog input signal reappears at the lead. The
duration of the
according to the following equation:
The CS8140 with its unique integration of linear regulator
and control features:
provides a single IC solution for a microprocessor power
supply. The reset delay, reset duration and watchdog fre-
quency limits are all determined by a single capacitor. For
a particular microprocessor the overriding requirement is
usually the reset delay (also known as power on reset).
The capacitor is chosen to meet this requirement and the
reset duration and watchdog frequency follow.
The reset delay is given by:
RESET
RESET
RESET
lead (Figure 3) until the correct Watchdog input
signal and the POWER-ON-
t
f
t
f
t
t
WDILOWER
WDI(UPPER)
WDI(
POR(typ)
WDI(LOWER)
WDI(UPPER)
function is activated when the Watchdog sig-
RESET
OUT
RESET
DELAY
= (4.75 x 10
)
CS8140 Design Example
= (1.3 x 10
-4.5% for more than 2µs (Figure 4b.)
= (1 x10
= (2.62 x 10
= (3.82 x 10
= (7.69 x 10
RESET
RESET
also determines the frequency of the
pulse is determined by C
RESET
4
)C
5
, ENABLE and WATCHDOG,
)C
5
)C
OUT
Function
DELAY
-5
DELAY
-4
)C
lead (Figure 3) until the
DELAY
-6
)C
)C
will be at 5V (typ). If
DELAY
DELAY
DELAY
RESET
or
-1
-1
or
DELAY
(POR) delay
Circuit Description: continued
DELAY
. The lim-
Application Notes
OUT
8
4a: Power
4b: Undervoltage Triggered
If an undervoltage condition exists, the voltage on the
discharged.
tion, the voltage on C
threshold and the Watchdog input signal is within its set
window limits (Figure 4). The delay after the output is in
regulation is:
The
external cap C
The output of the reset circuit is an open collector NPN.
its delay are governed by comparators with hysteresis to
avoid undesirable oscillations.
Assume that the reset delay must be 200ms minimum.
From the CS8140 data sheet the reset delay has a ±37% tol-
erance due to the regulator.
Assume the capacitor tolerance is ±10%.
Closest standard value is 0.82µF.
Minimum and maximum delays using 0.82µF are 220ms
and 586ms.
RESET
RESET
V
V
OUT
R
PEAK
RESET
-4.5%
RESET Circuit Waveforms with Delays Indicated
RESET
RESET
V
OUT
5V
V
V
V
t
lead goes low and the delay capacitor, C
is operational down to V
OUT
R
R
t
POR
RESET
HI
LO
POR(typ)
delay circuit is also programmed with the
(min) = (4.75 x 10
RESET
V
R
LO
DELAY
and Power Down
= (4.75 x 10
C
C
DELAY
<2mS
DELAY
.
remains low until output is in regula-
DELAY
RESET
(min) =
= (min) = 0.743 µF
³2ms
t
POR
exceeds the upper switching
5
) C
5
x 0.63) x C
DELAY
t
2.69 x 10
OUT
POR
= 1V. Both
(min)
t
POR
5
DELAY
x 0.9
RESET
DELAY
, is
and