FW82801E Intel, FW82801E Datasheet - Page 65

• Manufacturer Part Number: FW82801E
• Description: Communications I/O Controller Hub
• Manufacturer: Intel

Advance Information Datasheet
Table 45. IDE PIO & Multiword DMA Mode Timing (Sheet 2 of 2)
Table 46. Ultra ATA Timing (Mode 0, Mode 1, Mode 2)
NOTES:
NOTE:
Sym
1. IORDY is internally synchronized. This timing is to guarantee recognition on the next clock.
2. PIORDY sample point from DIOx# assertion and PDIOx# active pulse width is programmable from 2-5 PCI
3. PIORDY sample point from DIOx# assertion, PDIOx# active pulse width and PDIOx# inactive pulse width
4. PDIOx# inactive pulse width is programmable from 1-4 PCI clocks when the drive mode is Mode 2 or
1. The specification symbols in parentheses correspond to the Ultra ATA specification name.
t74
t75
t76
Sym
t80
t81
t82
t83
t84
t85
t86
t87
t88
t89
t90
t91
clocks when the drive mode is Mode 2 or greater. Refer to the ISP field in the IDE Timing Register
cycle time is the compatible timing when the drive mode is Mode 0/1. Refer to the TIM0/1 field in the IDE
timing register.
greater. Refer to the RCT field in the IDE Timing Register.
PIORDY/SIORDY Inactive Pulse Width
PDIOR#/PDIOW#/SDIOR#/SDIOW# Pulse Width
Low
PDIOR#/PDIOW#/SDIOR#/SDIOW# Pulse Width
High
Sustained Cycle Time (T2cyctyp)
Cycle Time (Tcyc)
Two Cycle Time (T2cyc)
Data Setup Time (Tds)
Data Hold Time (Tdh)
Data Valid Setup Time (Tdvs)
Data Valid Hold Time (Tdvh)
Limited Interlock Time (Tli)
Interlock Time w/ Minimum (Tmli)
Envelope Time (Tenv)
Ready to Pause Time (Trp)
DMACK setup/hold Time (Tack)
Parameter (1)
Parameter
Mode 0 (ns)
Min
230
160
112
15
70
20
20
20
5
6
0
240
Max
150
70
Min
48
Mode 1 (ns)
Min
154
125
73
10
48
20
20
20
5
6
0
160
Max
Max
150
70
Units
ns
Mode 2 (ns)
Min
115
100
54
30
20
20
20
Intel
7
5
6
0
120
Notes
®
2,3
3,4
Max
150
70
82801E C-ICH
Figure
15, 16
15, 16
Figure
17,
15
18
18
18
18
18
18
20
20
17
19
20
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