CY7C1329-75AC Cypress Semiconductor, CY7C1329-75AC Datasheet - Page 9

• Manufacturer Part Number: CY7C1329-75AC
• Description: 64K x 32 Synchronous-Pipelined Cache RAM
• Manufacturer: Cypress Semiconductor

Switching Waveforms
Write Cycle Timing
Notes:
14. WE is the combination of BWE, BW
15. WDx stands for Write Data to Address X.
CE
ADV
ADD
WE
CE
CE
CLK
ADSC
GW
OE
ADSP
Data-
In
1
2
3
t
t
t
CES
ADS
CES
t
AS
High-Z
t
CES
WD1
t
ADVS
[14, 15]
t
t
t
Single Write
ADH
CEH
t
ADS
DS
ADV Must Be Inactive for ADSP Write
t
CYC
t
t
t
CEH
CEH
t
AH
WS
1a
1a
t
t
t
ADVH
WH
t
DH
ADH
[3:0]
and GW to define a write cycle (see Write Cycle Descriptions table).
WD2
t
CH
= UNDEFINED
t
t
WS
CL
2a
t
WH
Burst Write
ADSP ignored with CE
2b
CE
1
9
masks ADSP
= DON’T CARE
2c
1
inactive
2d
ADSC initiated write
WD3
3a
Pipelined Write
Unselected with CE
High-Z
CY7C1329
Unselected
2