CY7C1329-100AI CYPRESS [Cypress Semiconductor], CY7C1329-100AI Datasheet

CY7C1329-100AI

Manufacturer Part Number

CY7C1329-100AI

Description

64K x 32 Synchronous-Pipelined Cache RAM

Manufacturer

CYPRESS [Cypress Semiconductor]

Datasheet

1.CY7C1329-100AI.pdf (15 pages)

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Cypress Semiconductor Corporation

Document #: 38-05279 Rev. *B

Features

Functional Description

The CY7C1329 is a 3.3V, 64K by 32 synchronous-pipelined

cache SRAM designed to support zero wait state secondary

cache with minimal glue logic.

Logic Block Diagram

• Supports 133-MHz bus for Pentium

• Fully registered inputs and outputs for pipelined

• 64K x 32 common I/O architecture

• Single 3.3V power supply

• Fast clock-to-output times

• User-selectable burst counter supporting Intel

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• JEDEC-standard 100-lead TQFP pinout

• “ZZ” Sleep Mode option and Stop Clock option

operations with zero wait states

operation

— 4.2 ns (for 133-MHz device)

— 5.5 ns (for 100-MHz device)

Pentium interleaved or linear burst sequences

ADSP

ADSC

ADV

BWE

[15:0]

CLK

64K x 32 Synchronous-Pipelined Cache RAM



MODE

and PowerPC

[1:0]

•

)

3901 North First Street

CLR

ENABLE DELAY

CLK

BYTEWRITE

REGISTERS

BYTEWRITE

REGISTERS

BYTEWRITE

REGISTERS

BYTEWRITE

DQ[23:16]

DQ[31:24]

COUNTER

DQ[15:8]

CONTROL

ADDRESS

DQ[7:0]

ENABLE

SLEEP

BURST



All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

Maximum access delay from the clock rise is 4.2 ns (133-MHz

device).

The CY7C1329 supports either the interleaved burst

sequence used by the Intel Pentium processor or a linear burst

sequence used by processors such as the PowerPC. The

burst sequence is selected through the MODE pin. Accesses

can be initiated by asserting either the Processor Address

Strobe (ADSP) or the Controller Address Strobe (ADSC) at

clock rise. Address advancement through the burst sequence

is controlled by the ADV input. A 2-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

Byte Write operations are qualified with the four Byte Write

Select (BW

all Byte Write inputs and writes data to all four bytes. All writes

are conducted with on-chip synchronous self-timed Write

circuitry.

Three synchronous Chip Selects (CE

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to provide

proper data during depth expansion, OE is masked during the

first clock of a Read cycle when emerging from a deselected

state.

•

[3:0]

) inputs. A Global Write Enable (GW) overrides

San Jose

CA 95134

CLK

REGISTERS

OUTPUT

64K × 32

Memory

Revised March 31, 2004

Array

, CE

•

CLK

CY7C1329

REGISTERS

408-943-2600

, CE

INPUT

) and an

[31:0]

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