CY7C1329-100AI CYPRESS [Cypress Semiconductor], CY7C1329-100AI Datasheet - Page 5

• Manufacturer Part Number: CY7C1329-100AI
• Description: 64K x 32 Synchronous-Pipelined Cache RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05279 Rev. *B
Interleaved Burst Sequence
Linear Burst Sequence
ZZ Mode Electrical Characteristics
Cycle Descriptions
I
t
t
Unselected
Unselected
Unselected
Unselected
Unselected
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
Notes:
DDZZ
ZZS
ZZREC
1. X = “Don't Care,” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BW
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
Parameter
Address
Address
Next Cycle
First
A
First
A
00
01
10
00
01
10
11
11
[1:0]
[1:0]
Snooze mode standby cur-
rent
Device operation to ZZ
ZZ recovery time
Address
Address
Second
Second
None
None
None
None
None
External
External
Next
Next
Next
Next
Current
Current
Current
Current
Current
A
A
Add. Used
01
00
10
01
10
00
11
11
[1:0]
[1:0]
Description
[1,2,3]
[3:0]
, and GW. See Write Cycle Descriptions table.
Address
Address
Third
Third
A
A
ZZ
10
00
01
10
00
01
11
11
[1:0]
[1:0]
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Test Conditions
ZZ > V
ZZ > V
CE
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
0
ZZ < 0.2V
3
Address
Address
Fourth
Fourth
A
A
DD
DD
10
01
00
00
01
10
11
11
[1:0]
[1:0]
CE
− 0.2V
− 0.2V
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
2
CE
0
0
X
X
X
X
1
1
X
1
0
0
0
0
1
1
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW.
1
2t
Min.
ADSP
CYC
X
X
0
0
1
1
0
1
1
1
X
X
1
1
X
1
ADSC
X
0
X
X
0
0
0
1
1
1
1
1
1
1
1
1
1
, CE
2t
ADV
Max.
2
X
X
X
X
X
X
X
CYC
0
0
0
0
1
1
1
1
1
3
, CE
3,
ZZREC
ADSP, and ADSC must
OE
X
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
CY7C1329
after the ZZ input
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Page 5 of 15
Unit
mA
ns
ns
X
X
X
X
X
X
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write