CY7C1329-100AI CYPRESS [Cypress Semiconductor], CY7C1329-100AI Datasheet - Page 9

• Manufacturer Part Number: CY7C1329-100AI
• Description: 64K x 32 Synchronous-Pipelined Cache RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05279 Rev. *B
Switching Waveforms
Write Cycle Timing
Notes:
14. WE is the combination of BWE, BW
15. WDx stands for Write Data to Address X.
ADD
CE
CE
ADSC
ADV
WE
CE
OE
CLK
ADSP
GW
Data-
In
1
2
3
t
t
t
CES
ADS
CES
t
AS
High-Z
t
CES
WD1
[14, 15]
t
ADVS
t
t
t
Single Write
ADH
t
CEH
ADS
DS
ADV Must Be Inactive for ADSP Write
t
t
CYC
t
t
CEH
t
CEH
AH
WS
1a
1a
[3:0]
t
t
t
t
ADVH
WH
DH
ADH
and GW to define a Write cycle (see Write Cycle Descriptions table).
WD2
t
CH
= UNDEFINED
t
WS
t
CL
2a
t
WH
Burst Write
ADSP ignored with CE
2b
CE
1
masks ADSP
= DON’T CARE
2c
1
inactive
2d
ADSC initiated Write
WD3
3a
Pipelined Write
Unselected with CE
High-Z
Unselected
2
CY7C1329
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