CY7C1329-100AI CYPRESS [Cypress Semiconductor], CY7C1329-100AI Datasheet - Page 11

• Manufacturer Part Number: CY7C1329-100AI
• Description: 64K x 32 Synchronous-Pipelined Cache RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05279 Rev. *B
Switching Waveforms
Read/Write Cycle Timing
Note:
17. Data bus is driven by SRAM, but data is not guaranteed.
CLK
ADSP
ADV
GW
CE
Data-
In/Out
WE
CE
CE
ADSC
OE
ADD
2
3
1
t
t
t
CES
ADS
CES
t
AS
t
CES
RD1
t
ADVS
Single Read
t
CEH
t
t
CYC
t
t
t
t
CEH
CEH
ADH
AH
WS
[14,15,16, 17]
t
t
OELZ
t
WH
t
CO
t
ADVH
ADS
(continued)
t
DOE
WD2
1a
Out
1a
t
Single Write
CH
t
t
OEHZ
ADH
t
CL
= DON’T CARE
2a
In
t
RD3
WS
t
WH
See Note 17
ADSP ignored with CE
2a
Out
= UNDEFINED
CE
Burst Read
1
t
masks ADSP
DS
3a
Out
t
DH
Out
3b
1
inactive
Pipelined Read
Out
3c
t
DOH
Out
3d
Unselected
T
CHZ
CY7C1329
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