CAT24WC01 Catalyst Semiconductor, CAT24WC01 Datasheet
CAT24WC01
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CAT24WC01 Summary of contents
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... Page Write Buffer DESCRIPTION The CAT24WC01/02/04/08/ 1K/2K/4K/8K/16K- 2 bit Serial CMOS E PROM internally organized as 128/ 256/512/1024/2048 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces de- vice power requirements. The the CAT24WC01/02/04/ PIN CONFIGURATION DIP Package (P) SOIC Package ( ...
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ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. – +125 C Storage Temperature ....................... – +150 C Voltage on Any Pin with (1) Respect to Ground ........... –2. with Respect to Ground ............... –2.0V ...
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A.C. CHARACTERISTICS V = +1.8V to +6.0V, unless otherwise specified. CC Read & Write Cycle Limits Symbol Parameter F Clock Frequency SCL (1) T Noise Suppression Time I Constant at SCL, SDA Inputs t SCL Low to SDA Data Out ...
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... Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24WC01/ 02/04/08/16 operates as a Slave device. Both the Mas- ter and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated ...
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... CAT24WC01/02/04/08/16 (see Fig. 5). The next three significant bits (A2, A1, A0) are the device address bits and define which device or which part of the device the Master is accessing eight CAT24WC01/ 02, four CAT24WC04, two CAT24WC08, and one CAT24WC16 may be individually addressed by the system ...
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... Master device. Page Write The CAT24WC01/02/04/08/16 writes bytes of data in a single write cycle, using the Page Write operation. The Page Write operation is initiated in the same manner as counter will ‘wrap around’ to address ...
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... This involves issuing the start condition followed by the slave address for a write operation. CAT24WC01/02/04/08/16 is still busy with the write operation, no ACK will be returned. If the CAT24WC01/ 02/04/08/16 has completed the write operation, an ACK will be returned and the host can then proceed with thenext read or write operation ...
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... Master device resends the START condition and the slave address, this time with the R/W bit set to one. The CAT24WC01/02/04/08/16 then re- sponds with its acknowledge and sends the 8-bit byte requested. The master device does not send an ac- knowledge but will generate a STOP condition ...
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Figure 9. Selective Read Timing BUS ACTIVITY: SLAVE R MASTER ADDRESS T SDA LINE Don't Care for 24WC01 Figure 10. Sequential Read Timing BUS ACTIVITY: SLAVE MASTER ADDRESS SDA LINE ORDERING ...