CAT24WC01 Catalyst Semiconductor, CAT24WC01 Datasheet - Page 4

• Manufacturer Part Number: CAT24WC01
• Description: 1K/2K/4K/8K/16K-Bit Serial E2PROM
• Manufacturer: Catalyst Semiconductor

FUNCTIONAL DESCRIPTION
The CAT24WC01/02/04/08/16 supports the I
data transmission protocol. This Inter-Integrated Circuit
Bus protocol defines any device that sends data to the
bus to be a transmitter and any device receiving data to
be a receiver. Data transfer is controlled by the Master
device which generates the serial clock and all START
and STOP conditions for bus access. The CAT24WC01/
02/04/08/16 operates as a Slave device. Both the Mas-
ter and Slave devices can operate as either transmitter
or receiver, but the Master device controls which mode
is activated. A maximum of 8 devices (24WC01 and
24WC02), 4 devices (24WC04), 2 devices (24WC08)
and 1 device (24WC16) may be connected to the bus as
determined by the device address inputs A0, A1, and A2.
Figure 1. Bus Timing
Figure 2. Write Cycle Timing
Figure 3. Start/Stop Timing
Doc. No. 25051-00 3/98 S-1
SDA OUT
SDA IN
SCL
SCL
SDA
t SU:STA
SDA
SCL
t F
8TH BIT
BYTE n
t HD:STA
t LOW
START BIT
t AA
ACK
t HD:DAT
t HIGH
2
C Bus
t LOW
STOP
CONDITION
4
t DH
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT24WC01/02/04/08/16 serial clock input pin is
used to clock all data transfers into or out of the device.
This is an input pin.
SDA: Serial Data/Address
The CAT24WC01/02/04/08/16 bidirectional serial data/
address pin is used to transfer data into and out of the
device. The SDA pin is an open drain output and can be
wire-ORed with other open drain or open collector
outputs.
A0, A1, A2: Device Address Inputs
These inputs set device address when cascading mul-
tiple devices. When these pins are left floating the
default values are zeros (except for the 24WC01).
A maximum of eight devices can be cascaded when
t SU:DAT
t R
t WR
START
CONDITION
STOP BIT
t SU:STO
t BUF
ADDRESS
5020 FHD F03
5020 FHD F04
5020 FHD F05