M29W400 ST Microelectronics, M29W400 Datasheet - Page 18

• Manufacturer Part Number: M29W400
• Description: 4 Mbit 512Kb x8 or 256Kb x16 / Boot Block Low Voltage Single Supply Flash Memory
• Manufacturer: ST Microelectronics

M29W400T, M29W400B
Table 15B. Write AC Characteristics, Write Enable Controlled
(T
Notes: 1. Sample only, not 100% tested.
Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address AAAAh
in the Byte-wide configuration or address 5555h in
the Word-wide configurationon third cycle after the
two Coded cycles. The Block Erase Confirm com-
mand 30h is similarly written on the sixth cycle after
another two Coded cycles. During the input of the
second command an address within the blockto be
erased is given and latched into the memory. Addi-
tional block Erase Confirm commands and block
addresses can be written subsequently to erase
other blocks in parallel, without further Coded cy-
cles. The erase will start after the erase timeout
period (see Erase Timer Bit DQ3 description).
Thus, additional Erase Confirm commands for
18/34
t
PHPHH
A
Symbol
t
t
WHRL
PHWL
t
t
t
t
t
t
t
t
t
t
t
VCHEL
WHGL
t
t
WHWL
WLWH
DVWH
WHDX
WHEH
GHWL
= 0 to 70 C, –20 to 85 C or –40 to 85 C)
AVWL
WLAX
ELWL
PLPX
AVAV
2. This timing is for Temporary Block Unprotection operation.
(1,2)
(1)
(1)
t
t
t
t
t
BUSY
t
t
t
WPH
VIDR
Alt
t
t
t
t
t
t
OEH
t
VCS
RSP
WC
WP
CS
DS
DH
CH
AS
AH
RP
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Address Valid to Write Enable Low
Write Enable Low to Address Transition
Output Enable High to Write Enable Low
V
Write Enable High to Output Enable Low
RP Rise Time to V
RP Pulse Width
Program Erase Valid to RB Delay
RP High to Write Enable Low
CC
High to Chip Enable Low
Parameter
ID
other blocks must be given within this delay. The
input of a new Erase Confirm command will restart
the timeout period. The status of the internal timer
can be monitored through the level of DQ3, if DQ3
is ’0’ the Block Erase Command has been given
and the timeout is running, if DQ3 is ’1’, the timeout
has expired and the P/E.C. is erasing the Block(s).
If the second command given is not an erase
confirm or if the Coded cycles are wrong, the
instruction aborts, and the device is reset to Read
Array. It is not necessary to program the block with
00h as the P/E.C. will do this automatically before
to erasing to FFh. Read operations after the sixth
rising edge of W or E output the status register
status bits.
V
CC
Min
120
500
500
50
50
30
50
50
0
0
0
0
0
0
4
= 2.7V to 3.6V
-120
M29W400T / M29W400B
Max
90
V
CC
Min
150
500
500
65
65
35
65
50
0
0
0
0
0
0
4
= 2.7V to 3.6V
-150
Max
90
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s