M29W400DT ST Microelectronics, M29W400DT Datasheet - Page 10

• Manufacturer Part Number: M29W400DT
• Description: 4 Mbit (512Kb x8 or 256Kb x16 / Boot Block) 3V Supply Flash Memory
• Manufacturer: ST Microelectronics

M29W400DT, M29W400DB
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A17). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Data Inputs/Outputs (DQ8-DQ14). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
is High, V
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, V
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to include this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
t
10/36
PLPX
. After Reset/Block Temporary Unprotect
IH
, all other pins are ignored.
IH
. When BYTE is Low, V
IL
, this pin behaves as an address
IH
, this pin behaves as a
IL
IL
, for at least
, these pins
goes High, V
Read and Bus Write operations after t
t
Output section, Table 15 and Figure 15, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
t
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 15 and Figure
15, Reset/Temporary Unprotect AC Characteris-
tics.
During Program or Erase operations Ready/Busy
is Low, V
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the 8-bit and 16-bit Bus modes of
the memory. When Byte/Word Organization Se-
lect is Low, V
it is High, V
V
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
Supply Voltage is less than the Lockout Voltage,
V
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
V
all voltage measurements.
RHEL
PHPHH
CC
LKO
SS
Ground. The V
Supply Voltage. The V
. This prevents Bus Write operations from ac-
, whichever occurs last. See the Ready/Busy
CC
.
Supply Voltage pin and the V
OL
IH
. Ready/Busy will remain Low during
IH
IL
, the memory is in 16-bit mode.
, the memory is in 8-bit mode, when
, the memory will be ready for Bus
ID
CC3
will temporarily unprotect the
SS
IH
.
to V
Ground is the reference for
ID
must be slower than
CC
Supply Voltage
SS
PHEL
Ground
CC
or