W83194R-17A Winbond, W83194R-17A Datasheet - Page 16

• Manufacturer Part Number: W83194R-17A
• Description: 100MHZ AGP CLOCK FOR SIS CHIPSET
• Manufacturer: Winbond

10.0 POWER MANAGEMENT TIMING
10.1 CPU_STOP# Timing Diagram
For synchronous Chipset, CPU_STOP# pin is a synchronous “ active low ” input pin used to stop the
CPU clocks for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while
the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume
output with full pulse width. In this case, CPU “ c locks on latency “ is less than 2 CPU clocks and
“c locks off latency ” is less then 2 CPU clocks.
10.2 PCI_STOP# Timing Diagram
For synchronous Chipset, PCI_STOP# pin is a synchronous “ a ctive low ” input pin used to stop the
PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while
the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output
with full pulse width. In this case, PCI “ c locks on latency “ is less than 1 PCI clocks and “ c locks off
latency ” is less then 1 PCI clocks.
CPUCLK[0:3]
CPU_STOP#
PCI_STOP#
PCICLK[0:4]
PCICLK_F
PCICLK_F
CPUCLK
CPUCLK
(Internal)
(Internal)
(Internal)
(Internal)
PCICLK
PCICLK
SDRAM
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1
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Publication Release Date: Sep. 1998
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W83194R-17/-17A
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PRELIMINARY
Revision 0.20