CY7C1480V33 Cypress Semiconductor, CY7C1480V33 Datasheet - Page 21

• Manufacturer Part Number: CY7C1480V33
• Description: (CY7C1480V33 / CY7C1482V33 / CY7C1486V33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
• Manufacturer: Cypress Semiconductor

Document #: 38-05283 Rev. *C
Switching Characteristics
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Set-up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Shaded areas contain advance information.
Notes:
15. This part has a voltage regulator internally; t
16. t
17. At any given voltage and temperature, t
18. This parameter is sampled and not 100% tested.
19. Timing reference level is 1.5V when V
20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
POWER
CYC
CH
CL
CO
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ADS
ADVS
WES
DS
CES
AH
ADH
ADVH
WEH
DH
CEH
Parameter
can be initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
CHZ
, t
CLZ
,t
OELZ
, and t
OEHZ
V
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
Clock to High-Z
OE LOW to Output Valid
OE LOW to Output Low-Z
OE HIGH to Output High-Z
Address Set-up Before CLK Rise
ADSC, ADSP Set-up Before CLK Rise
ADV Set-up Before CLK Rise
GW, BWE, BW
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
GW, BWE, BW
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
DD
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
(Typical) to the first access
DDQ
OEHZ
Over the Operating Range
[16, 17, 18]
X
X
[16, 17, 18]
= 3.3V and is 1.25V when V
POWER
Hold After CLK Rise
Set-up Before CLK Rise
Description
is less than t
is the time that the power needs to be supplied above V
[16, 17, 18]
[16, 17, 18]
OELZ
PRELIMINARY
[15]
and t
CHZ
[19, 20]
DDQ
is less than t
= 2.5V.
CLZ
Min.
4.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
0
250 MHz
to eliminate bus contention between SRAMs when sharing the same
Max.
3.0
3.0
3.0
3.0
DD
Min.
5.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
(minimum) initially before a read or write operation
1
0
200 MHz
Max.
3.0
3.0
3.0
3.0
CY7C1482V33
CY7C1486V33
Min.
CY7C1480V33
6.0
2.4
2.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
0
167 MHz
Max.
3.4
3.4
3.4
3.4
Page 21 of 30
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns