CY7C1480V33 Cypress Semiconductor, CY7C1480V33 Datasheet - Page 24

• Manufacturer Part Number: CY7C1480V33
• Description: (CY7C1480V33 / CY7C1482V33 / CY7C1486V33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
• Manufacturer: Cypress Semiconductor

Document #: 38-05283 Rev. *C
Switching Waveforms
Read/Write Cycle Timing
Notes:
23. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
24. GW is HIGH.
Data Out (Q)
Data In (D)
ADDRESS
ADSP
ADSC
BWE,
BW
ADV
CLK
OE
CE
X
A1
High-Z
High-Z
t ADS
t CES
t AS
A2
t ADH
t CEH
t CH
t AH
Back-to-Back READs
t CYC
t CLZ
[21, 23, 24]
Q(A1)
t CL
(continued)
t CO
Q(A2)
t OEHZ
t WES
t DS
D(A3)
Single WRITE
A3
t DH
t WEH
PRELIMINARY
DON’T CARE
A4
t OELZ
UNDEFINED
Q(A4)
BURST READ
Q(A4+1)
Q(A4+2)
Q(A4+3)
CY7C1482V33
CY7C1486V33
CY7C1480V33
D(A5)
A5
Page 24 of 30
Back-to-Back
WRITEs
D(A6)
A6